1/*
2 * Copyright (c) 2000-2012 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31
32#include <mach_kdp.h>
33#include <kdp/kdp_internal.h>
34#include <mach_ldebug.h>
35#include <gprof.h>
36
37#include <mach/mach_types.h>
38#include <mach/kern_return.h>
39
40#include <kern/kern_types.h>
41#include <kern/startup.h>
42#include <kern/timer_queue.h>
43#include <kern/processor.h>
44#include <kern/cpu_number.h>
45#include <kern/cpu_data.h>
46#include <kern/assert.h>
47#include <kern/machine.h>
48#include <kern/pms.h>
49#include <kern/misc_protos.h>
50#include <kern/timer_call.h>
51#include <kern/kalloc.h>
52#include <kern/queue.h>
53#include <prng/random.h>
54
55#include <vm/vm_map.h>
56#include <vm/vm_kern.h>
57
58#include <profiling/profile-mk.h>
59
60#include <i386/bit_routines.h>
61#include <i386/proc_reg.h>
62#include <i386/cpu_threads.h>
63#include <i386/mp_desc.h>
64#include <i386/misc_protos.h>
65#include <i386/trap.h>
66#include <i386/postcode.h>
67#include <i386/machine_routines.h>
68#include <i386/mp.h>
69#include <i386/mp_events.h>
70#include <i386/lapic.h>
71#include <i386/cpuid.h>
72#include <i386/fpu.h>
73#include <i386/machine_cpu.h>
74#include <i386/pmCPU.h>
75#if CONFIG_MCA
76#include <i386/machine_check.h>
77#endif
78#include <i386/acpi.h>
79
80#include <sys/kdebug.h>
81
82#include <console/serial_protos.h>
83
84#if MONOTONIC
85#include <kern/monotonic.h>
86#endif /* MONOTONIC */
87
88#if MP_DEBUG
89#define PAUSE delay(1000000)
90#define DBG(x...) kprintf(x)
91#else
92#define DBG(x...)
93#define PAUSE
94#endif /* MP_DEBUG */
95
96/* Debugging/test trace events: */
97#define TRACE_MP_TLB_FLUSH MACHDBG_CODE(DBG_MACH_MP, 0)
98#define TRACE_MP_CPUS_CALL MACHDBG_CODE(DBG_MACH_MP, 1)
99#define TRACE_MP_CPUS_CALL_LOCAL MACHDBG_CODE(DBG_MACH_MP, 2)
100#define TRACE_MP_CPUS_CALL_ACTION MACHDBG_CODE(DBG_MACH_MP, 3)
101#define TRACE_MP_CPUS_CALL_NOBUF MACHDBG_CODE(DBG_MACH_MP, 4)
102#define TRACE_MP_CPU_FAST_START MACHDBG_CODE(DBG_MACH_MP, 5)
103#define TRACE_MP_CPU_START MACHDBG_CODE(DBG_MACH_MP, 6)
104#define TRACE_MP_CPU_DEACTIVATE MACHDBG_CODE(DBG_MACH_MP, 7)
105
106#define ABS(v) (((v) > 0)?(v):-(v))
107
108void slave_boot_init(void);
109void i386_cpu_IPI(int cpu);
110
111#if MACH_KDP
112static void mp_kdp_wait(boolean_t flush, boolean_t isNMI);
113#endif /* MACH_KDP */
114
115#if MACH_KDP
116static boolean_t cpu_signal_pending(int cpu, mp_event_t event);
117#endif /* MACH_KDP */
118static int NMIInterruptHandler(x86_saved_state_t *regs);
119
120boolean_t smp_initialized = FALSE;
121uint32_t TSC_sync_margin = 0xFFF;
122volatile boolean_t force_immediate_debugger_NMI = FALSE;
123volatile boolean_t pmap_tlb_flush_timeout = FALSE;
124#if DEBUG || DEVELOPMENT
125boolean_t mp_interrupt_watchdog_enabled = TRUE;
126uint32_t mp_interrupt_watchdog_events = 0;
127#endif
128
129decl_simple_lock_data(,debugger_callback_lock);
130struct debugger_callback *debugger_callback = NULL;
131
132decl_lck_mtx_data(static, mp_cpu_boot_lock);
133lck_mtx_ext_t mp_cpu_boot_lock_ext;
134
135/* Variables needed for MP rendezvous. */
136decl_simple_lock_data(,mp_rv_lock);
137static void (*mp_rv_setup_func)(void *arg);
138static void (*mp_rv_action_func)(void *arg);
139static void (*mp_rv_teardown_func)(void *arg);
140static void *mp_rv_func_arg;
141static volatile int mp_rv_ncpus;
142 /* Cache-aligned barriers: */
143static volatile long mp_rv_entry __attribute__((aligned(64)));
144static volatile long mp_rv_exit __attribute__((aligned(64)));
145static volatile long mp_rv_complete __attribute__((aligned(64)));
146
147volatile uint64_t debugger_entry_time;
148volatile uint64_t debugger_exit_time;
149#if MACH_KDP
150#include <kdp/kdp.h>
151extern int kdp_snapshot;
152static struct _kdp_xcpu_call_func {
153 kdp_x86_xcpu_func_t func;
154 void *arg0, *arg1;
155 volatile long ret;
156 volatile uint16_t cpu;
157} kdp_xcpu_call_func = {
158 .cpu = KDP_XCPU_NONE
159};
160
161#endif
162
163/* Variables needed for MP broadcast. */
164static void (*mp_bc_action_func)(void *arg);
165static void *mp_bc_func_arg;
166static int mp_bc_ncpus;
167static volatile long mp_bc_count;
168decl_lck_mtx_data(static, mp_bc_lock);
169lck_mtx_ext_t mp_bc_lock_ext;
170static volatile int debugger_cpu = -1;
171volatile long NMIPI_acks = 0;
172volatile long NMI_count = 0;
173static NMI_reason_t NMI_panic_reason = NONE;
174static int vector_timed_out;
175
176extern void NMI_cpus(void);
177
178static void mp_cpus_call_init(void);
179static void mp_cpus_call_action(void);
180static void mp_call_PM(void);
181
182char mp_slave_stack[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE))); // Temp stack for slave init
183
184/* PAL-related routines */
185boolean_t i386_smp_init(int nmi_vector, i386_intr_func_t nmi_handler,
186 int ipi_vector, i386_intr_func_t ipi_handler);
187void i386_start_cpu(int lapic_id, int cpu_num);
188void i386_send_NMI(int cpu);
189void NMIPI_enable(boolean_t);
190#if GPROF
191/*
192 * Initialize dummy structs for profiling. These aren't used but
193 * allows hertz_tick() to be built with GPROF defined.
194 */
195struct profile_vars _profile_vars;
196struct profile_vars *_profile_vars_cpus[MAX_CPUS] = { &_profile_vars };
197#define GPROF_INIT() \
198{ \
199 int i; \
200 \
201 /* Hack to initialize pointers to unused profiling structs */ \
202 for (i = 1; i < MAX_CPUS; i++) \
203 _profile_vars_cpus[i] = &_profile_vars; \
204}
205#else
206#define GPROF_INIT()
207#endif /* GPROF */
208
209static lck_grp_t smp_lck_grp;
210static lck_grp_attr_t smp_lck_grp_attr;
211
212#define NUM_CPU_WARM_CALLS 20
213struct timer_call cpu_warm_call_arr[NUM_CPU_WARM_CALLS];
214queue_head_t cpu_warm_call_list;
215decl_simple_lock_data(static, cpu_warm_lock);
216
217typedef struct cpu_warm_data {
218 timer_call_t cwd_call;
219 uint64_t cwd_deadline;
220 int cwd_result;
221} *cpu_warm_data_t;
222
223static void cpu_prewarm_init(void);
224static void cpu_warm_timer_call_func(call_entry_param_t p0, call_entry_param_t p1);
225static void _cpu_warm_setup(void *arg);
226static timer_call_t grab_warm_timer_call(void);
227static void free_warm_timer_call(timer_call_t call);
228
229void
230smp_init(void)
231{
232 simple_lock_init(&mp_rv_lock, 0);
233 simple_lock_init(&debugger_callback_lock, 0);
234 lck_grp_attr_setdefault(&smp_lck_grp_attr);
235 lck_grp_init(&smp_lck_grp, "i386_smp", &smp_lck_grp_attr);
236 lck_mtx_init_ext(&mp_cpu_boot_lock, &mp_cpu_boot_lock_ext, &smp_lck_grp, LCK_ATTR_NULL);
237 lck_mtx_init_ext(&mp_bc_lock, &mp_bc_lock_ext, &smp_lck_grp, LCK_ATTR_NULL);
238 console_init();
239
240 if(!i386_smp_init(LAPIC_NMI_INTERRUPT, NMIInterruptHandler,
241 LAPIC_VECTOR(INTERPROCESSOR), cpu_signal_handler))
242 return;
243
244 cpu_thread_init();
245
246 GPROF_INIT();
247 DBGLOG_CPU_INIT(master_cpu);
248
249 mp_cpus_call_init();
250 mp_cpus_call_cpu_init(master_cpu);
251
252#if DEBUG || DEVELOPMENT
253 if (PE_parse_boot_argn("interrupt_watchdog",
254 &mp_interrupt_watchdog_enabled,
255 sizeof(mp_interrupt_watchdog_enabled))) {
256 kprintf("Interrupt watchdog %sabled\n",
257 mp_interrupt_watchdog_enabled ? "en" : "dis");
258 }
259#endif
260
261 if (PE_parse_boot_argn("TSC_sync_margin",
262 &TSC_sync_margin, sizeof(TSC_sync_margin))) {
263 kprintf("TSC sync Margin 0x%x\n", TSC_sync_margin);
264 } else if (cpuid_vmm_present()) {
265 kprintf("TSC sync margin disabled\n");
266 TSC_sync_margin = 0;
267 }
268 smp_initialized = TRUE;
269
270 cpu_prewarm_init();
271
272 return;
273}
274
275typedef struct {
276 int target_cpu;
277 int target_lapic;
278 int starter_cpu;
279} processor_start_info_t;
280static processor_start_info_t start_info __attribute__((aligned(64)));
281
282/*
283 * Cache-alignment is to avoid cross-cpu false-sharing interference.
284 */
285static volatile long tsc_entry_barrier __attribute__((aligned(64)));
286static volatile long tsc_exit_barrier __attribute__((aligned(64)));
287static volatile uint64_t tsc_target __attribute__((aligned(64)));
288
289/*
290 * Poll a CPU to see when it has marked itself as running.
291 */
292static void
293mp_wait_for_cpu_up(int slot_num, unsigned int iters, unsigned int usecdelay)
294{
295 while (iters-- > 0) {
296 if (cpu_datap(slot_num)->cpu_running)
297 break;
298 delay(usecdelay);
299 }
300}
301
302/*
303 * Quickly bring a CPU back online which has been halted.
304 */
305kern_return_t
306intel_startCPU_fast(int slot_num)
307{
308 kern_return_t rc;
309
310 /*
311 * Try to perform a fast restart
312 */
313 rc = pmCPUExitHalt(slot_num);
314 if (rc != KERN_SUCCESS)
315 /*
316 * The CPU was not eligible for a fast restart.
317 */
318 return(rc);
319
320 KERNEL_DEBUG_CONSTANT(
321 TRACE_MP_CPU_FAST_START | DBG_FUNC_START,
322 slot_num, 0, 0, 0, 0);
323
324 /*
325 * Wait until the CPU is back online.
326 */
327 mp_disable_preemption();
328
329 /*
330 * We use short pauses (1us) for low latency. 30,000 iterations is
331 * longer than a full restart would require so it should be more
332 * than long enough.
333 */
334
335 mp_wait_for_cpu_up(slot_num, 30000, 1);
336 mp_enable_preemption();
337
338 KERNEL_DEBUG_CONSTANT(
339 TRACE_MP_CPU_FAST_START | DBG_FUNC_END,
340 slot_num, cpu_datap(slot_num)->cpu_running, 0, 0, 0);
341
342 /*
343 * Check to make sure that the CPU is really running. If not,
344 * go through the slow path.
345 */
346 if (cpu_datap(slot_num)->cpu_running)
347 return(KERN_SUCCESS);
348 else
349 return(KERN_FAILURE);
350}
351
352static void
353started_cpu(void)
354{
355 /* Here on the started cpu with cpu_running set TRUE */
356
357 if (TSC_sync_margin &&
358 start_info.target_cpu == cpu_number()) {
359 /*
360 * I've just started-up, synchronize again with the starter cpu
361 * and then snap my TSC.
362 */
363 tsc_target = 0;
364 atomic_decl(&tsc_entry_barrier, 1);
365 while (tsc_entry_barrier != 0)
366 ; /* spin for starter and target at barrier */
367 tsc_target = rdtsc64();
368 atomic_decl(&tsc_exit_barrier, 1);
369 }
370}
371
372static void
373start_cpu(void *arg)
374{
375 int i = 1000;
376 processor_start_info_t *psip = (processor_start_info_t *) arg;
377
378 /* Ignore this if the current processor is not the starter */
379 if (cpu_number() != psip->starter_cpu)
380 return;
381
382 DBG("start_cpu(%p) about to start cpu %d, lapic %d\n",
383 arg, psip->target_cpu, psip->target_lapic);
384
385 KERNEL_DEBUG_CONSTANT(
386 TRACE_MP_CPU_START | DBG_FUNC_START,
387 psip->target_cpu,
388 psip->target_lapic, 0, 0, 0);
389
390 i386_start_cpu(psip->target_lapic, psip->target_cpu);
391
392#ifdef POSTCODE_DELAY
393 /* Wait much longer if postcodes are displayed for a delay period. */
394 i *= 10000;
395#endif
396 DBG("start_cpu(%p) about to wait for cpu %d\n",
397 arg, psip->target_cpu);
398
399 mp_wait_for_cpu_up(psip->target_cpu, i*100, 100);
400
401 KERNEL_DEBUG_CONSTANT(
402 TRACE_MP_CPU_START | DBG_FUNC_END,
403 psip->target_cpu,
404 cpu_datap(psip->target_cpu)->cpu_running, 0, 0, 0);
405
406 if (TSC_sync_margin &&
407 cpu_datap(psip->target_cpu)->cpu_running) {
408 /*
409 * Compare the TSC from the started processor with ours.
410 * Report and log/panic if it diverges by more than
411 * TSC_sync_margin (TSC_SYNC_MARGIN) ticks. This margin
412 * can be overriden by boot-arg (with 0 meaning no checking).
413 */
414 uint64_t tsc_starter;
415 int64_t tsc_delta;
416 atomic_decl(&tsc_entry_barrier, 1);
417 while (tsc_entry_barrier != 0)
418 ; /* spin for both processors at barrier */
419 tsc_starter = rdtsc64();
420 atomic_decl(&tsc_exit_barrier, 1);
421 while (tsc_exit_barrier != 0)
422 ; /* spin for target to store its TSC */
423 tsc_delta = tsc_target - tsc_starter;
424 kprintf("TSC sync for cpu %d: 0x%016llx delta 0x%llx (%lld)\n",
425 psip->target_cpu, tsc_target, tsc_delta, tsc_delta);
426 if (ABS(tsc_delta) > (int64_t) TSC_sync_margin) {
427#if DEBUG
428 panic(
429#else
430 printf(
431#endif
432 "Unsynchronized TSC for cpu %d: "
433 "0x%016llx, delta 0x%llx\n",
434 psip->target_cpu, tsc_target, tsc_delta);
435 }
436 }
437}
438
439kern_return_t
440intel_startCPU(
441 int slot_num)
442{
443 int lapic = cpu_to_lapic[slot_num];
444 boolean_t istate;
445
446 assert(lapic != -1);
447
448 DBGLOG_CPU_INIT(slot_num);
449
450 DBG("intel_startCPU(%d) lapic_id=%d\n", slot_num, lapic);
451 DBG("IdlePTD(%p): 0x%x\n", &IdlePTD, (int) (uintptr_t)IdlePTD);
452
453 /*
454 * Initialize (or re-initialize) the descriptor tables for this cpu.
455 * Propagate processor mode to slave.
456 */
457 cpu_desc_init(cpu_datap(slot_num));
458
459 /* Serialize use of the slave boot stack, etc. */
460 lck_mtx_lock(&mp_cpu_boot_lock);
461
462 istate = ml_set_interrupts_enabled(FALSE);
463 if (slot_num == get_cpu_number()) {
464 ml_set_interrupts_enabled(istate);
465 lck_mtx_unlock(&mp_cpu_boot_lock);
466 return KERN_SUCCESS;
467 }
468
469 start_info.starter_cpu = cpu_number();
470 start_info.target_cpu = slot_num;
471 start_info.target_lapic = lapic;
472 tsc_entry_barrier = 2;
473 tsc_exit_barrier = 2;
474
475 /*
476 * Perform the processor startup sequence with all running
477 * processors rendezvous'ed. This is required during periods when
478 * the cache-disable bit is set for MTRR/PAT initialization.
479 */
480 mp_rendezvous_no_intrs(start_cpu, (void *) &start_info);
481
482 start_info.target_cpu = 0;
483
484 ml_set_interrupts_enabled(istate);
485 lck_mtx_unlock(&mp_cpu_boot_lock);
486
487 if (!cpu_datap(slot_num)->cpu_running) {
488 kprintf("Failed to start CPU %02d\n", slot_num);
489 printf("Failed to start CPU %02d, rebooting...\n", slot_num);
490 delay(1000000);
491 halt_cpu();
492 return KERN_SUCCESS;
493 } else {
494 kprintf("Started cpu %d (lapic id %08x)\n", slot_num, lapic);
495 return KERN_SUCCESS;
496 }
497}
498
499#if MP_DEBUG
500cpu_signal_event_log_t *cpu_signal[MAX_CPUS];
501cpu_signal_event_log_t *cpu_handle[MAX_CPUS];
502
503MP_EVENT_NAME_DECL();
504
505#endif /* MP_DEBUG */
506
507/*
508 * Note: called with NULL state when polling for TLB flush and cross-calls.
509 */
510int
511cpu_signal_handler(x86_saved_state_t *regs)
512{
513#if !MACH_KDP
514#pragma unused (regs)
515#endif /* !MACH_KDP */
516 int my_cpu;
517 volatile int *my_word;
518
519 SCHED_STATS_IPI(current_processor());
520
521 my_cpu = cpu_number();
522 my_word = &cpu_data_ptr[my_cpu]->cpu_signals;
523 /* Store the initial set of signals for diagnostics. New
524 * signals could arrive while these are being processed
525 * so it's no more than a hint.
526 */
527
528 cpu_data_ptr[my_cpu]->cpu_prior_signals = *my_word;
529
530 do {
531#if MACH_KDP
532 if (i_bit(MP_KDP, my_word)) {
533 DBGLOG(cpu_handle,my_cpu,MP_KDP);
534 i_bit_clear(MP_KDP, my_word);
535/* Ensure that the i386_kernel_state at the base of the
536 * current thread's stack (if any) is synchronized with the
537 * context at the moment of the interrupt, to facilitate
538 * access through the debugger.
539 */
540 sync_iss_to_iks(regs);
541 if (pmsafe_debug && !kdp_snapshot)
542 pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
543 mp_kdp_wait(TRUE, FALSE);
544 if (pmsafe_debug && !kdp_snapshot)
545 pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_NORMAL);
546 } else
547#endif /* MACH_KDP */
548 if (i_bit(MP_TLB_FLUSH, my_word)) {
549 DBGLOG(cpu_handle,my_cpu,MP_TLB_FLUSH);
550 i_bit_clear(MP_TLB_FLUSH, my_word);
551 pmap_update_interrupt();
552 } else if (i_bit(MP_CALL, my_word)) {
553 DBGLOG(cpu_handle,my_cpu,MP_CALL);
554 i_bit_clear(MP_CALL, my_word);
555 mp_cpus_call_action();
556 } else if (i_bit(MP_CALL_PM, my_word)) {
557 DBGLOG(cpu_handle,my_cpu,MP_CALL_PM);
558 i_bit_clear(MP_CALL_PM, my_word);
559 mp_call_PM();
560 }
561 if (regs == NULL) {
562 /* Called to poll only for cross-calls and TLB flush */
563 break;
564 } else if (i_bit(MP_AST, my_word)) {
565 DBGLOG(cpu_handle,my_cpu,MP_AST);
566 i_bit_clear(MP_AST, my_word);
567 ast_check(cpu_to_processor(my_cpu));
568 }
569 } while (*my_word);
570
571 return 0;
572}
573
574extern void kprintf_break_lock(void);
575int
576NMIInterruptHandler(x86_saved_state_t *regs)
577{
578 void *stackptr;
579 char pstr[192];
580 uint64_t now = mach_absolute_time();
581
582 if (panic_active() && !panicDebugging) {
583 if (pmsafe_debug)
584 pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
585 for(;;)
586 cpu_pause();
587 }
588
589 atomic_incl(&NMIPI_acks, 1);
590 atomic_incl(&NMI_count, 1);
591 sync_iss_to_iks_unconditionally(regs);
592 __asm__ volatile("movq %%rbp, %0" : "=m" (stackptr));
593
594 if (cpu_number() == debugger_cpu)
595 goto NMExit;
596
597 if (NMI_panic_reason == SPINLOCK_TIMEOUT) {
598 snprintf(&pstr[0], sizeof(pstr),
599 "Panic(CPU %d, time %llu): NMIPI for spinlock acquisition timeout, spinlock: %p, spinlock owner: %p, current_thread: %p, spinlock_owner_cpu: 0x%x\n",
600 cpu_number(), now, spinlock_timed_out, (void *) spinlock_timed_out->interlock.lock_data, current_thread(), spinlock_owner_cpu);
601 panic_i386_backtrace(stackptr, 64, &pstr[0], TRUE, regs);
602 } else if (NMI_panic_reason == TLB_FLUSH_TIMEOUT) {
603 snprintf(&pstr[0], sizeof(pstr),
604 "Panic(CPU %d, time %llu): NMIPI for unresponsive processor: TLB flush timeout, TLB state:0x%x\n",
605 cpu_number(), now, current_cpu_datap()->cpu_tlb_invalid);
606 panic_i386_backtrace(stackptr, 48, &pstr[0], TRUE, regs);
607 } else if (NMI_panic_reason == CROSSCALL_TIMEOUT) {
608 snprintf(&pstr[0], sizeof(pstr),
609 "Panic(CPU %d, time %llu): NMIPI for unresponsive processor: cross-call timeout\n",
610 cpu_number(), now);
611 panic_i386_backtrace(stackptr, 64, &pstr[0], TRUE, regs);
612 } else if (NMI_panic_reason == INTERRUPT_WATCHDOG) {
613 snprintf(&pstr[0], sizeof(pstr),
614 "Panic(CPU %d, time %llu): NMIPI for unresponsive processor: interrupt watchdog for vector 0x%x\n",
615 cpu_number(), now, vector_timed_out);
616 panic_i386_backtrace(stackptr, 64, &pstr[0], TRUE, regs);
617 }
618
619#if MACH_KDP
620 if (pmsafe_debug && !kdp_snapshot)
621 pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
622 current_cpu_datap()->cpu_NMI_acknowledged = TRUE;
623 i_bit_clear(MP_KDP, &current_cpu_datap()->cpu_signals);
624 if (panic_active() || NMI_panic_reason != NONE) {
625 mp_kdp_wait(FALSE, TRUE);
626 } else if (!mp_kdp_trap &&
627 !mp_kdp_is_NMI &&
628 virtualized && (debug_boot_arg & DB_NMI)) {
629 /*
630 * Under a VMM with the debug boot-arg set, drop into kdp.
631 * Since an NMI is involved, there's a risk of contending with
632 * a panic. And side-effects of NMIs may result in entry into,
633 * and continuing from, the debugger being unreliable.
634 */
635 if (__sync_bool_compare_and_swap(&mp_kdp_is_NMI, FALSE, TRUE)) {
636 kprintf_break_lock();
637 kprintf("Debugger entry requested by NMI\n");
638 kdp_i386_trap(T_DEBUG, saved_state64(regs), 0, 0);
639 printf("Debugger entry requested by NMI\n");
640 mp_kdp_is_NMI = FALSE;
641 } else {
642 mp_kdp_wait(FALSE, FALSE);
643 }
644 } else {
645 mp_kdp_wait(FALSE, FALSE);
646 }
647 if (pmsafe_debug && !kdp_snapshot)
648 pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_NORMAL);
649#endif
650NMExit:
651 return 1;
652}
653
654
655/*
656 * cpu_interrupt is really just to be used by the scheduler to
657 * get a CPU's attention it may not always issue an IPI. If an
658 * IPI is always needed then use i386_cpu_IPI.
659 */
660void
661cpu_interrupt(int cpu)
662{
663 boolean_t did_IPI = FALSE;
664
665 if (smp_initialized
666 && pmCPUExitIdle(cpu_datap(cpu))) {
667 i386_cpu_IPI(cpu);
668 did_IPI = TRUE;
669 }
670
671 KERNEL_DEBUG_CONSTANT(MACHDBG_CODE(DBG_MACH_SCHED, MACH_REMOTE_AST), cpu, did_IPI, 0, 0, 0);
672}
673
674/*
675 * Send a true NMI via the local APIC to the specified CPU.
676 */
677void
678cpu_NMI_interrupt(int cpu)
679{
680 if (smp_initialized) {
681 i386_send_NMI(cpu);
682 }
683}
684
685void
686NMI_cpus(void)
687{
688 unsigned int cpu;
689 boolean_t intrs_enabled;
690 uint64_t tsc_timeout;
691
692 intrs_enabled = ml_set_interrupts_enabled(FALSE);
693 NMIPI_enable(TRUE);
694 for (cpu = 0; cpu < real_ncpus; cpu++) {
695 if (!cpu_is_running(cpu))
696 continue;
697 cpu_datap(cpu)->cpu_NMI_acknowledged = FALSE;
698 cpu_NMI_interrupt(cpu);
699 tsc_timeout = !machine_timeout_suspended() ?
700 rdtsc64() + (1000 * 1000 * 1000 * 10ULL) :
701 ~0ULL;
702 while (!cpu_datap(cpu)->cpu_NMI_acknowledged) {
703 handle_pending_TLB_flushes();
704 cpu_pause();
705 if (rdtsc64() > tsc_timeout)
706 panic("NMI_cpus() timeout cpu %d", cpu);
707 }
708 cpu_datap(cpu)->cpu_NMI_acknowledged = FALSE;
709 }
710 NMIPI_enable(FALSE);
711
712 ml_set_interrupts_enabled(intrs_enabled);
713}
714
715static void (* volatile mp_PM_func)(void) = NULL;
716
717static void
718mp_call_PM(void)
719{
720 assert(!ml_get_interrupts_enabled());
721
722 if (mp_PM_func != NULL)
723 mp_PM_func();
724}
725
726void
727cpu_PM_interrupt(int cpu)
728{
729 assert(!ml_get_interrupts_enabled());
730
731 if (mp_PM_func != NULL) {
732 if (cpu == cpu_number())
733 mp_PM_func();
734 else
735 i386_signal_cpu(cpu, MP_CALL_PM, ASYNC);
736 }
737}
738
739void
740PM_interrupt_register(void (*fn)(void))
741{
742 mp_PM_func = fn;
743}
744
745void
746i386_signal_cpu(int cpu, mp_event_t event, mp_sync_t mode)
747{
748 volatile int *signals = &cpu_datap(cpu)->cpu_signals;
749 uint64_t tsc_timeout;
750
751
752 if (!cpu_datap(cpu)->cpu_running)
753 return;
754
755 if (event == MP_TLB_FLUSH)
756 KERNEL_DEBUG(TRACE_MP_TLB_FLUSH | DBG_FUNC_START, cpu, 0, 0, 0, 0);
757
758 DBGLOG(cpu_signal, cpu, event);
759
760 i_bit_set(event, signals);
761 i386_cpu_IPI(cpu);
762 if (mode == SYNC) {
763 again:
764 tsc_timeout = !machine_timeout_suspended() ?
765 rdtsc64() + (1000*1000*1000) :
766 ~0ULL;
767 while (i_bit(event, signals) && rdtsc64() < tsc_timeout) {
768 cpu_pause();
769 }
770 if (i_bit(event, signals)) {
771 DBG("i386_signal_cpu(%d, 0x%x, SYNC) timed out\n",
772 cpu, event);
773 goto again;
774 }
775 }
776 if (event == MP_TLB_FLUSH)
777 KERNEL_DEBUG(TRACE_MP_TLB_FLUSH | DBG_FUNC_END, cpu, 0, 0, 0, 0);
778}
779
780/*
781 * Helper function called when busy-waiting: panic if too long
782 * a TSC-based time has elapsed since the start of the spin.
783 */
784static boolean_t
785mp_spin_timeout(uint64_t tsc_start)
786{
787 uint64_t tsc_timeout;
788
789 cpu_pause();
790 if (machine_timeout_suspended())
791 return FALSE;
792
793 /*
794 * The timeout is 4 * the spinlock timeout period
795 * unless we have serial console printing (kprintf) enabled
796 * in which case we allow an even greater margin.
797 */
798 tsc_timeout = disable_serial_output ? LockTimeOutTSC << 2
799 : LockTimeOutTSC << 4;
800 return (rdtsc64() > tsc_start + tsc_timeout);
801}
802
803/*
804 * Helper function to take a spinlock while ensuring that incoming IPIs
805 * are still serviced if interrupts are masked while we spin.
806 * Returns current interrupt state.
807 */
808boolean_t
809mp_safe_spin_lock(usimple_lock_t lock)
810{
811 if (ml_get_interrupts_enabled()) {
812 simple_lock(lock);
813 return TRUE;
814 } else {
815 uint64_t tsc_spin_start = rdtsc64();
816 while (!simple_lock_try(lock)) {
817 cpu_signal_handler(NULL);
818 if (mp_spin_timeout(tsc_spin_start)) {
819 uint32_t lock_cpu;
820 uintptr_t lowner = (uintptr_t)
821 lock->interlock.lock_data;
822 spinlock_timed_out = lock;
823 lock_cpu = spinlock_timeout_NMI(lowner);
824 NMIPI_panic(cpu_to_cpumask(lock_cpu), SPINLOCK_TIMEOUT);
825 panic("mp_safe_spin_lock() timed out, lock: %p, owner thread: 0x%lx, current_thread: %p, owner on CPU 0x%x, time: %llu",
826 lock, lowner, current_thread(), lock_cpu, mach_absolute_time());
827 }
828 }
829 return FALSE;
830 }
831}
832
833/*
834 * All-CPU rendezvous:
835 * - CPUs are signalled,
836 * - all execute the setup function (if specified),
837 * - rendezvous (i.e. all cpus reach a barrier),
838 * - all execute the action function (if specified),
839 * - rendezvous again,
840 * - execute the teardown function (if specified), and then
841 * - resume.
842 *
843 * Note that the supplied external functions _must_ be reentrant and aware
844 * that they are running in parallel and in an unknown lock context.
845 */
846
847static void
848mp_rendezvous_action(__unused void *null)
849{
850 boolean_t intrs_enabled;
851 uint64_t tsc_spin_start;
852
853 /*
854 * Note that mp_rv_lock was acquired by the thread that initiated the
855 * rendezvous and must have been acquired before we enter
856 * mp_rendezvous_action().
857 */
858 current_cpu_datap()->cpu_rendezvous_in_progress = TRUE;
859
860 /* setup function */
861 if (mp_rv_setup_func != NULL)
862 mp_rv_setup_func(mp_rv_func_arg);
863
864 intrs_enabled = ml_get_interrupts_enabled();
865
866 /* spin on entry rendezvous */
867 atomic_incl(&mp_rv_entry, 1);
868 tsc_spin_start = rdtsc64();
869
870 while (mp_rv_entry < mp_rv_ncpus) {
871 /* poll for pesky tlb flushes if interrupts disabled */
872 if (!intrs_enabled)
873 handle_pending_TLB_flushes();
874 if (mp_spin_timeout(tsc_spin_start)) {
875 panic("mp_rv_action() entry: %ld of %d responses, start: 0x%llx, cur: 0x%llx", mp_rv_entry, mp_rv_ncpus, tsc_spin_start, rdtsc64());
876 }
877 }
878
879 /* action function */
880 if (mp_rv_action_func != NULL)
881 mp_rv_action_func(mp_rv_func_arg);
882
883 /* spin on exit rendezvous */
884 atomic_incl(&mp_rv_exit, 1);
885 tsc_spin_start = rdtsc64();
886 while (mp_rv_exit < mp_rv_ncpus) {
887 if (!intrs_enabled)
888 handle_pending_TLB_flushes();
889 if (mp_spin_timeout(tsc_spin_start))
890 panic("mp_rv_action() exit: %ld of %d responses, start: 0x%llx, cur: 0x%llx", mp_rv_exit, mp_rv_ncpus, tsc_spin_start, rdtsc64());
891 }
892
893 /* teardown function */
894 if (mp_rv_teardown_func != NULL)
895 mp_rv_teardown_func(mp_rv_func_arg);
896
897 current_cpu_datap()->cpu_rendezvous_in_progress = FALSE;
898
899 /* Bump completion count */
900 atomic_incl(&mp_rv_complete, 1);
901}
902
903void
904mp_rendezvous(void (*setup_func)(void *),
905 void (*action_func)(void *),
906 void (*teardown_func)(void *),
907 void *arg)
908{
909 uint64_t tsc_spin_start;
910
911 if (!smp_initialized) {
912 if (setup_func != NULL)
913 setup_func(arg);
914 if (action_func != NULL)
915 action_func(arg);
916 if (teardown_func != NULL)
917 teardown_func(arg);
918 return;
919 }
920
921 /* obtain rendezvous lock */
922 mp_rendezvous_lock();
923
924 /* set static function pointers */
925 mp_rv_setup_func = setup_func;
926 mp_rv_action_func = action_func;
927 mp_rv_teardown_func = teardown_func;
928 mp_rv_func_arg = arg;
929
930 mp_rv_entry = 0;
931 mp_rv_exit = 0;
932 mp_rv_complete = 0;
933
934 /*
935 * signal other processors, which will call mp_rendezvous_action()
936 * with interrupts disabled
937 */
938 mp_rv_ncpus = mp_cpus_call(CPUMASK_OTHERS, NOSYNC, &mp_rendezvous_action, NULL) + 1;
939
940 /* call executor function on this cpu */
941 mp_rendezvous_action(NULL);
942
943 /*
944 * Spin for everyone to complete.
945 * This is necessary to ensure that all processors have proceeded
946 * from the exit barrier before we release the rendezvous structure.
947 */
948 tsc_spin_start = rdtsc64();
949 while (mp_rv_complete < mp_rv_ncpus) {
950 if (mp_spin_timeout(tsc_spin_start))
951 panic("mp_rendezvous() timeout: %ld of %d responses, start: 0x%llx, cur: 0x%llx", mp_rv_complete, mp_rv_ncpus, tsc_spin_start, rdtsc64());
952 }
953
954 /* Tidy up */
955 mp_rv_setup_func = NULL;
956 mp_rv_action_func = NULL;
957 mp_rv_teardown_func = NULL;
958 mp_rv_func_arg = NULL;
959
960 /* release lock */
961 mp_rendezvous_unlock();
962}
963
964void
965mp_rendezvous_lock(void)
966{
967 (void) mp_safe_spin_lock(&mp_rv_lock);
968}
969
970void
971mp_rendezvous_unlock(void)
972{
973 simple_unlock(&mp_rv_lock);
974}
975
976void
977mp_rendezvous_break_lock(void)
978{
979 simple_lock_init(&mp_rv_lock, 0);
980}
981
982static void
983setup_disable_intrs(__unused void * param_not_used)
984{
985 /* disable interrupts before the first barrier */
986 boolean_t intr = ml_set_interrupts_enabled(FALSE);
987
988 current_cpu_datap()->cpu_iflag = intr;
989 DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
990}
991
992static void
993teardown_restore_intrs(__unused void * param_not_used)
994{
995 /* restore interrupt flag following MTRR changes */
996 ml_set_interrupts_enabled(current_cpu_datap()->cpu_iflag);
997 DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
998}
999
1000/*
1001 * A wrapper to mp_rendezvous() to call action_func() with interrupts disabled.
1002 * This is exported for use by kexts.
1003 */
1004void
1005mp_rendezvous_no_intrs(
1006 void (*action_func)(void *),
1007 void *arg)
1008{
1009 mp_rendezvous(setup_disable_intrs,
1010 action_func,
1011 teardown_restore_intrs,
1012 arg);
1013}
1014
1015
1016typedef struct {
1017 queue_chain_t link; /* queue linkage */
1018 void (*func)(void *,void *); /* routine to call */
1019 void *arg0; /* routine's 1st arg */
1020 void *arg1; /* routine's 2nd arg */
1021 cpumask_t *maskp; /* completion response mask */
1022} mp_call_t;
1023
1024
1025typedef struct {
1026 queue_head_t queue;
1027 decl_simple_lock_data(, lock);
1028} mp_call_queue_t;
1029#define MP_CPUS_CALL_BUFS_PER_CPU MAX_CPUS
1030static mp_call_queue_t mp_cpus_call_freelist;
1031static mp_call_queue_t mp_cpus_call_head[MAX_CPUS];
1032
1033static inline boolean_t
1034mp_call_head_lock(mp_call_queue_t *cqp)
1035{
1036 boolean_t intrs_enabled;
1037
1038 intrs_enabled = ml_set_interrupts_enabled(FALSE);
1039 simple_lock(&cqp->lock);
1040
1041 return intrs_enabled;
1042}
1043
1044/*
1045 * Deliver an NMIPI to a set of processors to cause them to panic .
1046 */
1047void
1048NMIPI_panic(cpumask_t cpu_mask, NMI_reason_t why) {
1049 unsigned int cpu;
1050 cpumask_t cpu_bit;
1051 uint64_t deadline;
1052
1053 NMIPI_enable(TRUE);
1054 NMI_panic_reason = why;
1055
1056 for (cpu = 0, cpu_bit = 1; cpu < real_ncpus; cpu++, cpu_bit <<= 1) {
1057 if ((cpu_mask & cpu_bit) == 0)
1058 continue;
1059 cpu_datap(cpu)->cpu_NMI_acknowledged = FALSE;
1060 cpu_NMI_interrupt(cpu);
1061 }
1062
1063 /* Wait (only so long) for NMi'ed cpus to respond */
1064 deadline = mach_absolute_time() + LockTimeOut;
1065 for (cpu = 0, cpu_bit = 1; cpu < real_ncpus; cpu++, cpu_bit <<= 1) {
1066 if ((cpu_mask & cpu_bit) == 0)
1067 continue;
1068 while (!cpu_datap(cpu)->cpu_NMI_acknowledged &&
1069 mach_absolute_time() < deadline) {
1070 cpu_pause();
1071 }
1072 }
1073}
1074
1075#if MACH_ASSERT
1076static inline boolean_t
1077mp_call_head_is_locked(mp_call_queue_t *cqp)
1078{
1079 return !ml_get_interrupts_enabled() &&
1080 hw_lock_held((hw_lock_t)&cqp->lock);
1081}
1082#endif
1083
1084static inline void
1085mp_call_head_unlock(mp_call_queue_t *cqp, boolean_t intrs_enabled)
1086{
1087 simple_unlock(&cqp->lock);
1088 ml_set_interrupts_enabled(intrs_enabled);
1089}
1090
1091static inline mp_call_t *
1092mp_call_alloc(void)
1093{
1094 mp_call_t *callp = NULL;
1095 boolean_t intrs_enabled;
1096 mp_call_queue_t *cqp = &mp_cpus_call_freelist;
1097
1098 intrs_enabled = mp_call_head_lock(cqp);
1099 if (!queue_empty(&cqp->queue))
1100 queue_remove_first(&cqp->queue, callp, typeof(callp), link);
1101 mp_call_head_unlock(cqp, intrs_enabled);
1102
1103 return callp;
1104}
1105
1106static inline void
1107mp_call_free(mp_call_t *callp)
1108{
1109 boolean_t intrs_enabled;
1110 mp_call_queue_t *cqp = &mp_cpus_call_freelist;
1111
1112 intrs_enabled = mp_call_head_lock(cqp);
1113 queue_enter_first(&cqp->queue, callp, typeof(callp), link);
1114 mp_call_head_unlock(cqp, intrs_enabled);
1115}
1116
1117static inline mp_call_t *
1118mp_call_dequeue_locked(mp_call_queue_t *cqp)
1119{
1120 mp_call_t *callp = NULL;
1121
1122 assert(mp_call_head_is_locked(cqp));
1123 if (!queue_empty(&cqp->queue))
1124 queue_remove_first(&cqp->queue, callp, typeof(callp), link);
1125 return callp;
1126}
1127
1128static inline void
1129mp_call_enqueue_locked(
1130 mp_call_queue_t *cqp,
1131 mp_call_t *callp)
1132{
1133 queue_enter(&cqp->queue, callp, typeof(callp), link);
1134}
1135
1136/* Called on the boot processor to initialize global structures */
1137static void
1138mp_cpus_call_init(void)
1139{
1140 mp_call_queue_t *cqp = &mp_cpus_call_freelist;
1141
1142 DBG("mp_cpus_call_init()\n");
1143 simple_lock_init(&cqp->lock, 0);
1144 queue_init(&cqp->queue);
1145}
1146
1147/*
1148 * Called at processor registration to add call buffers to the free list
1149 * and to initialize the per-cpu call queue.
1150 */
1151void
1152mp_cpus_call_cpu_init(int cpu)
1153{
1154 int i;
1155 mp_call_queue_t *cqp = &mp_cpus_call_head[cpu];
1156 mp_call_t *callp;
1157
1158 simple_lock_init(&cqp->lock, 0);
1159 queue_init(&cqp->queue);
1160 for (i = 0; i < MP_CPUS_CALL_BUFS_PER_CPU; i++) {
1161 callp = (mp_call_t *) kalloc(sizeof(mp_call_t));
1162 mp_call_free(callp);
1163 }
1164
1165 DBG("mp_cpus_call_init(%d) done\n", cpu);
1166}
1167
1168/*
1169 * This is called from cpu_signal_handler() to process an MP_CALL signal.
1170 * And also from i386_deactivate_cpu() when a cpu is being taken offline.
1171 */
1172static void
1173mp_cpus_call_action(void)
1174{
1175 mp_call_queue_t *cqp;
1176 boolean_t intrs_enabled;
1177 mp_call_t *callp;
1178 mp_call_t call;
1179
1180 assert(!ml_get_interrupts_enabled());
1181 cqp = &mp_cpus_call_head[cpu_number()];
1182 intrs_enabled = mp_call_head_lock(cqp);
1183 while ((callp = mp_call_dequeue_locked(cqp)) != NULL) {
1184 /* Copy call request to the stack to free buffer */
1185 call = *callp;
1186 mp_call_free(callp);
1187 if (call.func != NULL) {
1188 mp_call_head_unlock(cqp, intrs_enabled);
1189 KERNEL_DEBUG_CONSTANT(
1190 TRACE_MP_CPUS_CALL_ACTION,
1191 VM_KERNEL_UNSLIDE(call.func), VM_KERNEL_UNSLIDE_OR_PERM(call.arg0),
1192 VM_KERNEL_UNSLIDE_OR_PERM(call.arg1), VM_KERNEL_ADDRPERM(call.maskp), 0);
1193 call.func(call.arg0, call.arg1);
1194 (void) mp_call_head_lock(cqp);
1195 }
1196 if (call.maskp != NULL)
1197 i_bit_set(cpu_number(), call.maskp);
1198 }
1199 mp_call_head_unlock(cqp, intrs_enabled);
1200}
1201
1202/*
1203 * mp_cpus_call() runs a given function on cpus specified in a given cpu mask.
1204 * Possible modes are:
1205 * SYNC: function is called serially on target cpus in logical cpu order
1206 * waiting for each call to be acknowledged before proceeding
1207 * ASYNC: function call is queued to the specified cpus
1208 * waiting for all calls to complete in parallel before returning
1209 * NOSYNC: function calls are queued
1210 * but we return before confirmation of calls completing.
1211 * The action function may be NULL.
1212 * The cpu mask may include the local cpu. Offline cpus are ignored.
1213 * The return value is the number of cpus on which the call was made or queued.
1214 */
1215cpu_t
1216mp_cpus_call(
1217 cpumask_t cpus,
1218 mp_sync_t mode,
1219 void (*action_func)(void *),
1220 void *arg)
1221{
1222 return mp_cpus_call1(
1223 cpus,
1224 mode,
1225 (void (*)(void *,void *))action_func,
1226 arg,
1227 NULL,
1228 NULL);
1229}
1230
1231static void
1232mp_cpus_call_wait(boolean_t intrs_enabled,
1233 cpumask_t cpus_called,
1234 cpumask_t *cpus_responded)
1235{
1236 mp_call_queue_t *cqp;
1237 uint64_t tsc_spin_start;
1238
1239 assert(ml_get_interrupts_enabled() == 0 || get_preemption_level() != 0);
1240 cqp = &mp_cpus_call_head[cpu_number()];
1241
1242 tsc_spin_start = rdtsc64();
1243 while (*cpus_responded != cpus_called) {
1244 if (!intrs_enabled) {
1245 /* Sniffing w/o locking */
1246 if (!queue_empty(&cqp->queue))
1247 mp_cpus_call_action();
1248 cpu_signal_handler(NULL);
1249 }
1250 if (mp_spin_timeout(tsc_spin_start)) {
1251 cpumask_t cpus_unresponsive;
1252
1253 cpus_unresponsive = cpus_called & ~(*cpus_responded);
1254 NMIPI_panic(cpus_unresponsive, CROSSCALL_TIMEOUT);
1255 panic("mp_cpus_call_wait() timeout, cpus: 0x%llx",
1256 cpus_unresponsive);
1257 }
1258 }
1259}
1260
1261cpu_t
1262mp_cpus_call1(
1263 cpumask_t cpus,
1264 mp_sync_t mode,
1265 void (*action_func)(void *, void *),
1266 void *arg0,
1267 void *arg1,
1268 cpumask_t *cpus_calledp)
1269{
1270 cpu_t cpu = 0;
1271 boolean_t intrs_enabled = FALSE;
1272 boolean_t call_self = FALSE;
1273 cpumask_t cpus_called = 0;
1274 cpumask_t cpus_responded = 0;
1275 long cpus_call_count = 0;
1276 uint64_t tsc_spin_start;
1277 boolean_t topo_lock;
1278
1279 KERNEL_DEBUG_CONSTANT(
1280 TRACE_MP_CPUS_CALL | DBG_FUNC_START,
1281 cpus, mode, VM_KERNEL_UNSLIDE(action_func), VM_KERNEL_UNSLIDE_OR_PERM(arg0), VM_KERNEL_UNSLIDE_OR_PERM(arg1));
1282
1283 if (!smp_initialized) {
1284 if ((cpus & CPUMASK_SELF) == 0)
1285 goto out;
1286 if (action_func != NULL) {
1287 intrs_enabled = ml_set_interrupts_enabled(FALSE);
1288 action_func(arg0, arg1);
1289 ml_set_interrupts_enabled(intrs_enabled);
1290 }
1291 call_self = TRUE;
1292 goto out;
1293 }
1294
1295 /*
1296 * Queue the call for each non-local requested cpu.
1297 * This is performed under the topo lock to prevent changes to
1298 * cpus online state and to prevent concurrent rendezvouses --
1299 * although an exception is made if we're calling only the master
1300 * processor since that always remains active. Note: this exception
1301 * is expected for longterm timer nosync cross-calls to the master cpu.
1302 */
1303 mp_disable_preemption();
1304 intrs_enabled = ml_get_interrupts_enabled();
1305 topo_lock = (cpus != cpu_to_cpumask(master_cpu));
1306 if (topo_lock) {
1307 ml_set_interrupts_enabled(FALSE);
1308 (void) mp_safe_spin_lock(&x86_topo_lock);
1309 }
1310 for (cpu = 0; cpu < (cpu_t) real_ncpus; cpu++) {
1311 if (((cpu_to_cpumask(cpu) & cpus) == 0) ||
1312 !cpu_is_running(cpu))
1313 continue;
1314 tsc_spin_start = rdtsc64();
1315 if (cpu == (cpu_t) cpu_number()) {
1316 /*
1317 * We don't IPI ourself and if calling asynchronously,
1318 * we defer our call until we have signalled all others.
1319 */
1320 call_self = TRUE;
1321 if (mode == SYNC && action_func != NULL) {
1322 KERNEL_DEBUG_CONSTANT(
1323 TRACE_MP_CPUS_CALL_LOCAL,
1324 VM_KERNEL_UNSLIDE(action_func),
1325 VM_KERNEL_UNSLIDE_OR_PERM(arg0), VM_KERNEL_UNSLIDE_OR_PERM(arg1), 0, 0);
1326 action_func(arg0, arg1);
1327 }
1328 } else {
1329 /*
1330 * Here to queue a call to cpu and IPI.
1331 */
1332 mp_call_t *callp = NULL;
1333 mp_call_queue_t *cqp = &mp_cpus_call_head[cpu];
1334 boolean_t intrs_inner;
1335
1336 queue_call:
1337 if (callp == NULL)
1338 callp = mp_call_alloc();
1339 intrs_inner = mp_call_head_lock(cqp);
1340 if (callp == NULL) {
1341 mp_call_head_unlock(cqp, intrs_inner);
1342 KERNEL_DEBUG_CONSTANT(
1343 TRACE_MP_CPUS_CALL_NOBUF,
1344 cpu, 0, 0, 0, 0);
1345 if (!intrs_inner) {
1346 /* Sniffing w/o locking */
1347 if (!queue_empty(&cqp->queue))
1348 mp_cpus_call_action();
1349 handle_pending_TLB_flushes();
1350 }
1351 if (mp_spin_timeout(tsc_spin_start))
1352 panic("mp_cpus_call1() timeout start: 0x%llx, cur: 0x%llx",
1353 tsc_spin_start, rdtsc64());
1354 goto queue_call;
1355 }
1356 callp->maskp = (mode == NOSYNC) ? NULL : &cpus_responded;
1357 callp->func = action_func;
1358 callp->arg0 = arg0;
1359 callp->arg1 = arg1;
1360 mp_call_enqueue_locked(cqp, callp);
1361 cpus_call_count++;
1362 cpus_called |= cpu_to_cpumask(cpu);
1363 i386_signal_cpu(cpu, MP_CALL, ASYNC);
1364 mp_call_head_unlock(cqp, intrs_inner);
1365 if (mode == SYNC) {
1366 mp_cpus_call_wait(intrs_inner, cpus_called, &cpus_responded);
1367 }
1368 }
1369 }
1370 if (topo_lock) {
1371 simple_unlock(&x86_topo_lock);
1372 ml_set_interrupts_enabled(intrs_enabled);
1373 }
1374
1375 /* Call locally if mode not SYNC */
1376 if (mode != SYNC && call_self ) {
1377 KERNEL_DEBUG_CONSTANT(
1378 TRACE_MP_CPUS_CALL_LOCAL,
1379 VM_KERNEL_UNSLIDE(action_func), VM_KERNEL_UNSLIDE_OR_PERM(arg0), VM_KERNEL_UNSLIDE_OR_PERM(arg1), 0, 0);
1380 if (action_func != NULL) {
1381 ml_set_interrupts_enabled(FALSE);
1382 action_func(arg0, arg1);
1383 ml_set_interrupts_enabled(intrs_enabled);
1384 }
1385 }
1386
1387 /* For ASYNC, now wait for all signaled cpus to complete their calls */
1388 if (mode == ASYNC)
1389 mp_cpus_call_wait(intrs_enabled, cpus_called, &cpus_responded);
1390
1391 /* Safe to allow pre-emption now */
1392 mp_enable_preemption();
1393
1394out:
1395 if (call_self){
1396 cpus_called |= cpu_to_cpumask(cpu);
1397 cpus_call_count++;
1398 }
1399
1400 if (cpus_calledp)
1401 *cpus_calledp = cpus_called;
1402
1403 KERNEL_DEBUG_CONSTANT(
1404 TRACE_MP_CPUS_CALL | DBG_FUNC_END,
1405 cpus_call_count, cpus_called, 0, 0, 0);
1406
1407 return (cpu_t) cpus_call_count;
1408}
1409
1410
1411static void
1412mp_broadcast_action(__unused void *null)
1413{
1414 /* call action function */
1415 if (mp_bc_action_func != NULL)
1416 mp_bc_action_func(mp_bc_func_arg);
1417
1418 /* if we're the last one through, wake up the instigator */
1419 if (atomic_decl_and_test(&mp_bc_count, 1))
1420 thread_wakeup(((event_t)(uintptr_t) &mp_bc_count));
1421}
1422
1423/*
1424 * mp_broadcast() runs a given function on all active cpus.
1425 * The caller blocks until the functions has run on all cpus.
1426 * The caller will also block if there is another pending braodcast.
1427 */
1428void
1429mp_broadcast(
1430 void (*action_func)(void *),
1431 void *arg)
1432{
1433 if (!smp_initialized) {
1434 if (action_func != NULL)
1435 action_func(arg);
1436 return;
1437 }
1438
1439 /* obtain broadcast lock */
1440 lck_mtx_lock(&mp_bc_lock);
1441
1442 /* set static function pointers */
1443 mp_bc_action_func = action_func;
1444 mp_bc_func_arg = arg;
1445
1446 assert_wait((event_t)(uintptr_t)&mp_bc_count, THREAD_UNINT);
1447
1448 /*
1449 * signal other processors, which will call mp_broadcast_action()
1450 */
1451 mp_bc_count = real_ncpus; /* assume max possible active */
1452 mp_bc_ncpus = mp_cpus_call(CPUMASK_OTHERS, NOSYNC, *mp_broadcast_action, NULL) + 1;
1453 atomic_decl(&mp_bc_count, real_ncpus - mp_bc_ncpus); /* subtract inactive */
1454
1455 /* call executor function on this cpu */
1456 mp_broadcast_action(NULL);
1457
1458 /* block for other cpus to have run action_func */
1459 if (mp_bc_ncpus > 1)
1460 thread_block(THREAD_CONTINUE_NULL);
1461 else
1462 clear_wait(current_thread(), THREAD_AWAKENED);
1463
1464 /* release lock */
1465 lck_mtx_unlock(&mp_bc_lock);
1466}
1467
1468void
1469mp_cpus_kick(cpumask_t cpus)
1470{
1471 cpu_t cpu;
1472 boolean_t intrs_enabled = FALSE;
1473
1474 intrs_enabled = ml_set_interrupts_enabled(FALSE);
1475 mp_safe_spin_lock(&x86_topo_lock);
1476
1477 for (cpu = 0; cpu < (cpu_t) real_ncpus; cpu++) {
1478 if ((cpu == (cpu_t) cpu_number())
1479 || ((cpu_to_cpumask(cpu) & cpus) == 0)
1480 || !cpu_is_running(cpu))
1481 {
1482 continue;
1483 }
1484
1485 lapic_send_ipi(cpu, LAPIC_VECTOR(KICK));
1486 }
1487
1488 simple_unlock(&x86_topo_lock);
1489 ml_set_interrupts_enabled(intrs_enabled);
1490}
1491
1492void
1493i386_activate_cpu(void)
1494{
1495 cpu_data_t *cdp = current_cpu_datap();
1496
1497 assert(!ml_get_interrupts_enabled());
1498
1499 if (!smp_initialized) {
1500 cdp->cpu_running = TRUE;
1501 return;
1502 }
1503
1504 mp_safe_spin_lock(&x86_topo_lock);
1505 cdp->cpu_running = TRUE;
1506 started_cpu();
1507 simple_unlock(&x86_topo_lock);
1508 flush_tlb_raw();
1509}
1510
1511void
1512i386_deactivate_cpu(void)
1513{
1514 cpu_data_t *cdp = current_cpu_datap();
1515
1516 assert(!ml_get_interrupts_enabled());
1517
1518 KERNEL_DEBUG_CONSTANT(
1519 TRACE_MP_CPU_DEACTIVATE | DBG_FUNC_START,
1520 0, 0, 0, 0, 0);
1521
1522 mp_safe_spin_lock(&x86_topo_lock);
1523 cdp->cpu_running = FALSE;
1524 simple_unlock(&x86_topo_lock);
1525
1526 /*
1527 * Move all of this cpu's timers to the master/boot cpu,
1528 * and poke it in case there's a sooner deadline for it to schedule.
1529 */
1530 timer_queue_shutdown(&cdp->rtclock_timer.queue);
1531 mp_cpus_call(cpu_to_cpumask(master_cpu), ASYNC, timer_queue_expire_local, NULL);
1532
1533#if MONOTONIC
1534 mt_cpu_down(cdp);
1535#endif /* MONOTONIC */
1536
1537 /*
1538 * Open an interrupt window
1539 * and ensure any pending IPI or timer is serviced
1540 */
1541 mp_disable_preemption();
1542 ml_set_interrupts_enabled(TRUE);
1543
1544 while (cdp->cpu_signals && x86_lcpu()->rtcDeadline != EndOfAllTime)
1545 cpu_pause();
1546 /*
1547 * Ensure there's no remaining timer deadline set
1548 * - AICPM may have left one active.
1549 */
1550 setPop(0);
1551
1552 ml_set_interrupts_enabled(FALSE);
1553 mp_enable_preemption();
1554
1555 KERNEL_DEBUG_CONSTANT(
1556 TRACE_MP_CPU_DEACTIVATE | DBG_FUNC_END,
1557 0, 0, 0, 0, 0);
1558}
1559
1560int pmsafe_debug = 1;
1561
1562#if MACH_KDP
1563volatile boolean_t mp_kdp_trap = FALSE;
1564volatile boolean_t mp_kdp_is_NMI = FALSE;
1565volatile unsigned long mp_kdp_ncpus;
1566boolean_t mp_kdp_state;
1567
1568
1569void
1570mp_kdp_enter(boolean_t proceed_on_failure)
1571{
1572 unsigned int cpu;
1573 unsigned int ncpus = 0;
1574 unsigned int my_cpu;
1575 uint64_t tsc_timeout;
1576
1577 DBG("mp_kdp_enter()\n");
1578
1579 /*
1580 * Here to enter the debugger.
1581 * In case of races, only one cpu is allowed to enter kdp after
1582 * stopping others.
1583 */
1584 mp_kdp_state = ml_set_interrupts_enabled(FALSE);
1585 my_cpu = cpu_number();
1586
1587 if (my_cpu == (unsigned) debugger_cpu) {
1588 kprintf("\n\nRECURSIVE DEBUGGER ENTRY DETECTED\n\n");
1589 kdp_reset();
1590 return;
1591 }
1592
1593 uint64_t start_time = cpu_datap(my_cpu)->debugger_entry_time = mach_absolute_time();
1594 int locked = 0;
1595 while (!locked || mp_kdp_trap) {
1596 if (locked) {
1597 simple_unlock(&x86_topo_lock);
1598 }
1599 if (proceed_on_failure) {
1600 if (mach_absolute_time() - start_time > 500000000ll) {
1601 paniclog_append_noflush("mp_kdp_enter() can't get x86_topo_lock! Debugging anyway! #YOLO\n");
1602 break;
1603 }
1604 locked = simple_lock_try(&x86_topo_lock);
1605 if (!locked) {
1606 cpu_pause();
1607 }
1608 } else {
1609 mp_safe_spin_lock(&x86_topo_lock);
1610 locked = TRUE;
1611 }
1612
1613 if (locked && mp_kdp_trap) {
1614 simple_unlock(&x86_topo_lock);
1615 DBG("mp_kdp_enter() race lost\n");
1616#if MACH_KDP
1617 mp_kdp_wait(TRUE, FALSE);
1618#endif
1619 locked = FALSE;
1620 }
1621 }
1622
1623 if (pmsafe_debug && !kdp_snapshot)
1624 pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
1625
1626 debugger_cpu = my_cpu;
1627 ncpus = 1;
1628 atomic_incl((volatile long *)&mp_kdp_ncpus, 1);
1629 mp_kdp_trap = TRUE;
1630 debugger_entry_time = cpu_datap(my_cpu)->debugger_entry_time;
1631
1632 /*
1633 * Deliver a nudge to other cpus, counting how many
1634 */
1635 DBG("mp_kdp_enter() signaling other processors\n");
1636 if (force_immediate_debugger_NMI == FALSE) {
1637 for (cpu = 0; cpu < real_ncpus; cpu++) {
1638 if (cpu == my_cpu || !cpu_is_running(cpu))
1639 continue;
1640 ncpus++;
1641 i386_signal_cpu(cpu, MP_KDP, ASYNC);
1642 }
1643 /*
1644 * Wait other processors to synchronize
1645 */
1646 DBG("mp_kdp_enter() waiting for (%d) processors to suspend\n", ncpus);
1647
1648 /*
1649 * This timeout is rather arbitrary; we don't want to NMI
1650 * processors that are executing at potentially
1651 * "unsafe-to-interrupt" points such as the trampolines,
1652 * but neither do we want to lose state by waiting too long.
1653 */
1654 tsc_timeout = rdtsc64() + (LockTimeOutTSC);
1655
1656 while (mp_kdp_ncpus != ncpus && rdtsc64() < tsc_timeout) {
1657 /*
1658 * A TLB shootdown request may be pending--this would
1659 * result in the requesting processor waiting in
1660 * PMAP_UPDATE_TLBS() until this processor deals with it.
1661 * Process it, so it can now enter mp_kdp_wait()
1662 */
1663 handle_pending_TLB_flushes();
1664 cpu_pause();
1665 }
1666 /* If we've timed out, and some processor(s) are still unresponsive,
1667 * interrupt them with an NMI via the local APIC, iff a panic is
1668 * in progress.
1669 */
1670 if (panic_active()) {
1671 NMIPI_enable(TRUE);
1672 }
1673 if (mp_kdp_ncpus != ncpus) {
1674 unsigned int wait_cycles = 0;
1675 if (proceed_on_failure)
1676 paniclog_append_noflush("mp_kdp_enter() timed-out on cpu %d, NMI-ing\n", my_cpu);
1677 else
1678 DBG("mp_kdp_enter() timed-out on cpu %d, NMI-ing\n", my_cpu);
1679 for (cpu = 0; cpu < real_ncpus; cpu++) {
1680 if (cpu == my_cpu || !cpu_is_running(cpu))
1681 continue;
1682 if (cpu_signal_pending(cpu, MP_KDP)) {
1683 cpu_datap(cpu)->cpu_NMI_acknowledged = FALSE;
1684 cpu_NMI_interrupt(cpu);
1685 }
1686 }
1687 /* Wait again for the same timeout */
1688 tsc_timeout = rdtsc64() + (LockTimeOutTSC);
1689 while (mp_kdp_ncpus != ncpus && rdtsc64() < tsc_timeout) {
1690 handle_pending_TLB_flushes();
1691 cpu_pause();
1692 ++wait_cycles;
1693 }
1694 if (mp_kdp_ncpus != ncpus) {
1695 paniclog_append_noflush("mp_kdp_enter() NMI pending on cpus:");
1696 for (cpu = 0; cpu < real_ncpus; cpu++) {
1697 if (cpu_is_running(cpu) && !cpu_datap(cpu)->cpu_NMI_acknowledged)
1698 paniclog_append_noflush(" %d", cpu);
1699 }
1700 paniclog_append_noflush("\n");
1701 if (proceed_on_failure) {
1702 paniclog_append_noflush("mp_kdp_enter() timed-out during %s wait after NMI;"
1703 "expected %u acks but received %lu after %u loops in %llu ticks\n",
1704 (locked ? "locked" : "unlocked"), ncpus, mp_kdp_ncpus, wait_cycles, LockTimeOutTSC);
1705 } else {
1706 panic("mp_kdp_enter() timed-out during %s wait after NMI;"
1707 "expected %u acks but received %lu after %u loops in %llu ticks",
1708 (locked ? "locked" : "unlocked"), ncpus, mp_kdp_ncpus, wait_cycles, LockTimeOutTSC);
1709 }
1710 }
1711 }
1712 }
1713 else
1714 for (cpu = 0; cpu < real_ncpus; cpu++) {
1715 if (cpu == my_cpu || !cpu_is_running(cpu))
1716 continue;
1717 cpu_NMI_interrupt(cpu);
1718 }
1719
1720 if (locked) {
1721 simple_unlock(&x86_topo_lock);
1722 }
1723
1724 DBG("mp_kdp_enter() %d processors done %s\n",
1725 (int)mp_kdp_ncpus, (mp_kdp_ncpus == ncpus) ? "OK" : "timed out");
1726
1727 postcode(MP_KDP_ENTER);
1728}
1729
1730boolean_t
1731mp_kdp_all_cpus_halted()
1732{
1733 unsigned int ncpus = 0, cpu = 0, my_cpu = 0;
1734
1735 my_cpu = cpu_number();
1736 ncpus = 1; /* current CPU */
1737 for (cpu = 0; cpu < real_ncpus; cpu++) {
1738 if (cpu == my_cpu || !cpu_is_running(cpu))
1739 continue;
1740 ncpus++;
1741 }
1742
1743 return (mp_kdp_ncpus == ncpus);
1744}
1745
1746static boolean_t
1747cpu_signal_pending(int cpu, mp_event_t event)
1748{
1749 volatile int *signals = &cpu_datap(cpu)->cpu_signals;
1750 boolean_t retval = FALSE;
1751
1752 if (i_bit(event, signals))
1753 retval = TRUE;
1754 return retval;
1755}
1756
1757long kdp_x86_xcpu_invoke(const uint16_t lcpu, kdp_x86_xcpu_func_t func,
1758 void *arg0, void *arg1)
1759{
1760 if (lcpu > (real_ncpus - 1))
1761 return -1;
1762
1763 if (func == NULL)
1764 return -1;
1765
1766 kdp_xcpu_call_func.func = func;
1767 kdp_xcpu_call_func.ret = -1;
1768 kdp_xcpu_call_func.arg0 = arg0;
1769 kdp_xcpu_call_func.arg1 = arg1;
1770 kdp_xcpu_call_func.cpu = lcpu;
1771 DBG("Invoking function %p on CPU %d\n", func, (int32_t)lcpu);
1772 while (kdp_xcpu_call_func.cpu != KDP_XCPU_NONE)
1773 cpu_pause();
1774 return kdp_xcpu_call_func.ret;
1775}
1776
1777static void
1778kdp_x86_xcpu_poll(void)
1779{
1780 if ((uint16_t)cpu_number() == kdp_xcpu_call_func.cpu) {
1781 kdp_xcpu_call_func.ret =
1782 kdp_xcpu_call_func.func(kdp_xcpu_call_func.arg0,
1783 kdp_xcpu_call_func.arg1,
1784 cpu_number());
1785 kdp_xcpu_call_func.cpu = KDP_XCPU_NONE;
1786 }
1787}
1788
1789static void
1790mp_kdp_wait(boolean_t flush, boolean_t isNMI)
1791{
1792 DBG("mp_kdp_wait()\n");
1793
1794 current_cpu_datap()->debugger_ipi_time = mach_absolute_time();
1795#if CONFIG_MCA
1796 /* If we've trapped due to a machine-check, save MCA registers */
1797 mca_check_save();
1798#endif
1799
1800 atomic_incl((volatile long *)&mp_kdp_ncpus, 1);
1801 while (mp_kdp_trap || (isNMI == TRUE)) {
1802 /*
1803 * A TLB shootdown request may be pending--this would result
1804 * in the requesting processor waiting in PMAP_UPDATE_TLBS()
1805 * until this processor handles it.
1806 * Process it, so it can now enter mp_kdp_wait()
1807 */
1808 if (flush)
1809 handle_pending_TLB_flushes();
1810
1811 kdp_x86_xcpu_poll();
1812 cpu_pause();
1813 }
1814
1815 atomic_decl((volatile long *)&mp_kdp_ncpus, 1);
1816 DBG("mp_kdp_wait() done\n");
1817}
1818
1819void
1820mp_kdp_exit(void)
1821{
1822 DBG("mp_kdp_exit()\n");
1823 debugger_cpu = -1;
1824 atomic_decl((volatile long *)&mp_kdp_ncpus, 1);
1825
1826 debugger_exit_time = mach_absolute_time();
1827
1828 mp_kdp_trap = FALSE;
1829 mfence();
1830
1831 /* Wait other processors to stop spinning. XXX needs timeout */
1832 DBG("mp_kdp_exit() waiting for processors to resume\n");
1833 while (mp_kdp_ncpus > 0) {
1834 /*
1835 * a TLB shootdown request may be pending... this would result in the requesting
1836 * processor waiting in PMAP_UPDATE_TLBS() until this processor deals with it.
1837 * Process it, so it can now enter mp_kdp_wait()
1838 */
1839 handle_pending_TLB_flushes();
1840
1841 cpu_pause();
1842 }
1843
1844 if (pmsafe_debug && !kdp_snapshot)
1845 pmSafeMode(&current_cpu_datap()->lcpu, PM_SAFE_FL_NORMAL);
1846
1847 debugger_exit_time = mach_absolute_time();
1848
1849 DBG("mp_kdp_exit() done\n");
1850 (void) ml_set_interrupts_enabled(mp_kdp_state);
1851 postcode(MP_KDP_EXIT);
1852}
1853
1854#endif /* MACH_KDP */
1855
1856boolean_t
1857mp_recent_debugger_activity(void) {
1858 uint64_t abstime = mach_absolute_time();
1859 return (((abstime - debugger_entry_time) < LastDebuggerEntryAllowance) ||
1860 ((abstime - debugger_exit_time) < LastDebuggerEntryAllowance));
1861}
1862
1863/*ARGSUSED*/
1864void
1865init_ast_check(
1866 __unused processor_t processor)
1867{
1868}
1869
1870void
1871cause_ast_check(
1872 processor_t processor)
1873{
1874 int cpu = processor->cpu_id;
1875
1876 if (cpu != cpu_number()) {
1877 i386_signal_cpu(cpu, MP_AST, ASYNC);
1878 KERNEL_DEBUG_CONSTANT(MACHDBG_CODE(DBG_MACH_SCHED, MACH_REMOTE_AST), cpu, 1, 0, 0, 0);
1879 }
1880}
1881
1882void
1883slave_machine_init(void *param)
1884{
1885 /*
1886 * Here in process context, but with interrupts disabled.
1887 */
1888 DBG("slave_machine_init() CPU%d\n", get_cpu_number());
1889
1890 if (param == FULL_SLAVE_INIT) {
1891 /*
1892 * Cold start
1893 */
1894 clock_init();
1895 }
1896 cpu_machine_init(); /* Interrupts enabled hereafter */
1897}
1898
1899#undef cpu_number
1900int cpu_number(void)
1901{
1902 return get_cpu_number();
1903}
1904
1905static void
1906cpu_prewarm_init()
1907{
1908 int i;
1909
1910 simple_lock_init(&cpu_warm_lock, 0);
1911 queue_init(&cpu_warm_call_list);
1912 for (i = 0; i < NUM_CPU_WARM_CALLS; i++) {
1913 enqueue_head(&cpu_warm_call_list, (queue_entry_t)&cpu_warm_call_arr[i]);
1914 }
1915}
1916
1917static timer_call_t
1918grab_warm_timer_call()
1919{
1920 spl_t x;
1921 timer_call_t call = NULL;
1922
1923 x = splsched();
1924 simple_lock(&cpu_warm_lock);
1925 if (!queue_empty(&cpu_warm_call_list)) {
1926 call = (timer_call_t) dequeue_head(&cpu_warm_call_list);
1927 }
1928 simple_unlock(&cpu_warm_lock);
1929 splx(x);
1930
1931 return call;
1932}
1933
1934static void
1935free_warm_timer_call(timer_call_t call)
1936{
1937 spl_t x;
1938
1939 x = splsched();
1940 simple_lock(&cpu_warm_lock);
1941 enqueue_head(&cpu_warm_call_list, (queue_entry_t)call);
1942 simple_unlock(&cpu_warm_lock);
1943 splx(x);
1944}
1945
1946/*
1947 * Runs in timer call context (interrupts disabled).
1948 */
1949static void
1950cpu_warm_timer_call_func(
1951 call_entry_param_t p0,
1952 __unused call_entry_param_t p1)
1953{
1954 free_warm_timer_call((timer_call_t)p0);
1955 return;
1956}
1957
1958/*
1959 * Runs with interrupts disabled on the CPU we wish to warm (i.e. CPU 0).
1960 */
1961static void
1962_cpu_warm_setup(
1963 void *arg)
1964{
1965 cpu_warm_data_t cwdp = (cpu_warm_data_t)arg;
1966
1967 timer_call_enter(cwdp->cwd_call, cwdp->cwd_deadline, TIMER_CALL_SYS_CRITICAL | TIMER_CALL_LOCAL);
1968 cwdp->cwd_result = 0;
1969
1970 return;
1971}
1972
1973/*
1974 * Not safe to call with interrupts disabled.
1975 */
1976kern_return_t
1977ml_interrupt_prewarm(
1978 uint64_t deadline)
1979{
1980 struct cpu_warm_data cwd;
1981 timer_call_t call;
1982 cpu_t ct;
1983
1984 if (ml_get_interrupts_enabled() == FALSE) {
1985 panic("%s: Interrupts disabled?\n", __FUNCTION__);
1986 }
1987
1988 /*
1989 * If the platform doesn't need our help, say that we succeeded.
1990 */
1991 if (!ml_get_interrupt_prewake_applicable()) {
1992 return KERN_SUCCESS;
1993 }
1994
1995 /*
1996 * Grab a timer call to use.
1997 */
1998 call = grab_warm_timer_call();
1999 if (call == NULL) {
2000 return KERN_RESOURCE_SHORTAGE;
2001 }
2002
2003 timer_call_setup(call, cpu_warm_timer_call_func, call);
2004 cwd.cwd_call = call;
2005 cwd.cwd_deadline = deadline;
2006 cwd.cwd_result = 0;
2007
2008 /*
2009 * For now, non-local interrupts happen on the master processor.
2010 */
2011 ct = mp_cpus_call(cpu_to_cpumask(master_cpu), SYNC, _cpu_warm_setup, &cwd);
2012 if (ct == 0) {
2013 free_warm_timer_call(call);
2014 return KERN_FAILURE;
2015 } else {
2016 return cwd.cwd_result;
2017 }
2018}
2019
2020#if DEBUG || DEVELOPMENT
2021void
2022kernel_spin(uint64_t spin_ns)
2023{
2024 boolean_t istate;
2025 uint64_t spin_abs;
2026 uint64_t deadline;
2027 cpu_data_t *cdp;
2028
2029 kprintf("kernel_spin(%llu) spinning uninterruptibly\n", spin_ns);
2030 istate = ml_set_interrupts_enabled(FALSE);
2031 cdp = current_cpu_datap();
2032 nanoseconds_to_absolutetime(spin_ns, &spin_abs);
2033
2034 /* Fake interrupt handler entry for testing mp_interrupt_watchdog() */
2035 cdp->cpu_int_event_time = mach_absolute_time();
2036 cdp->cpu_int_state = (void *) USER_STATE(current_thread());
2037
2038 deadline = mach_absolute_time() + spin_ns;
2039 while (mach_absolute_time() < deadline)
2040 cpu_pause();
2041
2042 cdp->cpu_int_event_time = 0;
2043 cdp->cpu_int_state = NULL;
2044
2045 ml_set_interrupts_enabled(istate);
2046 kprintf("kernel_spin() continuing\n");
2047}
2048
2049/*
2050 * Called from the scheduler's maintenance thread,
2051 * scan running processors for long-running ISRs and:
2052 * - panic if longer than LockTimeOut, or
2053 * - log if more than a quantum.
2054 */
2055void
2056mp_interrupt_watchdog(void)
2057{
2058 cpu_t cpu;
2059 boolean_t intrs_enabled = FALSE;
2060 uint16_t cpu_int_num;
2061 uint64_t cpu_int_event_time;
2062 uint64_t cpu_rip;
2063 uint64_t cpu_int_duration;
2064 uint64_t now;
2065 x86_saved_state_t *cpu_int_state;
2066
2067 if (__improbable(!mp_interrupt_watchdog_enabled))
2068 return;
2069
2070 intrs_enabled = ml_set_interrupts_enabled(FALSE);
2071 now = mach_absolute_time();
2072 /*
2073 * While timeouts are not suspended,
2074 * check all other processors for long outstanding interrupt handling.
2075 */
2076 for (cpu = 0;
2077 cpu < (cpu_t) real_ncpus && !machine_timeout_suspended();
2078 cpu++) {
2079 if ((cpu == (cpu_t) cpu_number()) ||
2080 (!cpu_is_running(cpu)))
2081 continue;
2082 cpu_int_event_time = cpu_datap(cpu)->cpu_int_event_time;
2083 if (cpu_int_event_time == 0)
2084 continue;
2085 if (__improbable(now < cpu_int_event_time))
2086 continue; /* skip due to inter-processor skew */
2087 cpu_int_state = cpu_datap(cpu)->cpu_int_state;
2088 if (__improbable(cpu_int_state == NULL))
2089 /* The interrupt may have been dismissed */
2090 continue;
2091
2092 /* Here with a cpu handling an interrupt */
2093
2094 cpu_int_duration = now - cpu_int_event_time;
2095 if (__improbable(cpu_int_duration > LockTimeOut)) {
2096 cpu_int_num = saved_state64(cpu_int_state)->isf.trapno;
2097 cpu_rip = saved_state64(cpu_int_state)->isf.rip;
2098 vector_timed_out = cpu_int_num;
2099 NMIPI_panic(cpu_to_cpumask(cpu), INTERRUPT_WATCHDOG);
2100 panic("Interrupt watchdog, "
2101 "cpu: %d interrupt: 0x%x time: %llu..%llu state: %p RIP: 0x%llx",
2102 cpu, cpu_int_num, cpu_int_event_time, now, cpu_int_state, cpu_rip);
2103 /* NOT REACHED */
2104 } else if (__improbable(cpu_int_duration > (uint64_t) std_quantum)) {
2105 mp_interrupt_watchdog_events++;
2106 cpu_int_num = saved_state64(cpu_int_state)->isf.trapno;
2107 cpu_rip = saved_state64(cpu_int_state)->isf.rip;
2108 ml_set_interrupts_enabled(intrs_enabled);
2109 printf("Interrupt watchdog, "
2110 "cpu: %d interrupt: 0x%x time: %llu..%llu RIP: 0x%llx\n",
2111 cpu, cpu_int_num, cpu_int_event_time, now, cpu_rip);
2112 return;
2113 }
2114 }
2115
2116 ml_set_interrupts_enabled(intrs_enabled);
2117}
2118#endif
2119