1 | /* |
2 | * CDDL HEADER START |
3 | * |
4 | * The contents of this file are subject to the terms of the |
5 | * Common Development and Distribution License, Version 1.0 only |
6 | * (the "License"). You may not use this file except in compliance |
7 | * with the License. |
8 | * |
9 | * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE |
10 | * or http://www.opensolaris.org/os/licensing. |
11 | * See the License for the specific language governing permissions |
12 | * and limitations under the License. |
13 | * |
14 | * When distributing Covered Code, include this CDDL HEADER in each |
15 | * file and include the License file at usr/src/OPENSOLARIS.LICENSE. |
16 | * If applicable, add the following below this CDDL HEADER, with the |
17 | * fields enclosed by brackets "[]" replaced with your own identifying |
18 | * information: Portions Copyright [yyyy] [name of copyright owner] |
19 | * |
20 | * CDDL HEADER END |
21 | */ |
22 | /* |
23 | * Copyright 2004 Sun Microsystems, Inc. All rights reserved. |
24 | * Use is subject to license terms. |
25 | */ |
26 | |
27 | /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ |
28 | |
29 | /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ |
30 | /* All Rights Reserved */ |
31 | |
32 | #ifndef _FASTTRAP_REGSET_H |
33 | #define _FASTTRAP_REGSET_H |
34 | |
35 | /* |
36 | * APPLE NOTE: This file was orginally uts/intel/sys/regset.h |
37 | */ |
38 | |
39 | /* |
40 | * #pragma ident "@(#)regset.h 1.11 05/06/08 SMI" |
41 | */ |
42 | |
43 | #ifdef __cplusplus |
44 | extern "C" { |
45 | #endif |
46 | |
47 | /* |
48 | * The names and offsets defined here should be specified by the |
49 | * AMD64 ABI suppl. |
50 | * |
51 | * We make fsbase and gsbase part of the lwp context (since they're |
52 | * the only way to access the full 64-bit address range via the segment |
53 | * registers) and thus belong here too. However we treat them as |
54 | * read-only; if %fs or %gs are updated, the results of the descriptor |
55 | * table lookup that those updates implicitly cause will be reflected |
56 | * in the corresponding fsbase and/or gsbase values the next time the |
57 | * context can be inspected. However it is NOT possible to override |
58 | * the fsbase/gsbase settings via this interface. |
59 | * |
60 | * Direct modification of the base registers (thus overriding the |
61 | * descriptor table base address) can be achieved with _lwp_setprivate. |
62 | */ |
63 | |
64 | #define REG_GSBASE 27 |
65 | #define REG_FSBASE 26 |
66 | #define REG_DS 25 |
67 | #define REG_ES 24 |
68 | |
69 | #define REG_GS 23 |
70 | #define REG_FS 22 |
71 | #define REG_SS 21 |
72 | #define REG_RSP 20 |
73 | #define REG_RFL 19 |
74 | #define REG_CS 18 |
75 | #define REG_RIP 17 |
76 | #define REG_ERR 16 |
77 | #define REG_TRAPNO 15 |
78 | #define REG_RAX 14 |
79 | #define REG_RCX 13 |
80 | #define REG_RDX 12 |
81 | #define REG_RBX 11 |
82 | #define REG_RBP 10 |
83 | #define REG_RSI 9 |
84 | #define REG_RDI 8 |
85 | #define REG_R8 7 |
86 | #define REG_R9 6 |
87 | #define REG_R10 5 |
88 | #define REG_R11 4 |
89 | #define REG_R12 3 |
90 | #define REG_R13 2 |
91 | #define REG_R14 1 |
92 | #define REG_R15 0 |
93 | |
94 | /* |
95 | * The names and offsets defined here are specified by i386 ABI suppl. |
96 | */ |
97 | |
98 | #define SS 18 /* only stored on a privilege transition */ |
99 | #define UESP 17 /* only stored on a privilege transition */ |
100 | #define EFL 16 |
101 | #define CS 15 |
102 | #define EIP 14 |
103 | #define ERR 13 |
104 | #define TRAPNO 12 |
105 | #define EAX 11 |
106 | #define ECX 10 |
107 | #define EDX 9 |
108 | #define EBX 8 |
109 | #define ESP 7 |
110 | #define EBP 6 |
111 | #define ESI 5 |
112 | #define EDI 4 |
113 | #define DS 3 |
114 | #define ES 2 |
115 | #define FS 1 |
116 | #define GS 0 |
117 | |
118 | #define REG_PC EIP |
119 | #define REG_FP EBP |
120 | #define REG_SP UESP |
121 | #define REG_PS EFL |
122 | #define REG_R0 EAX |
123 | #define REG_R1 EDX |
124 | |
125 | #ifdef __cplusplus |
126 | } |
127 | #endif |
128 | |
129 | #endif /* _FASTTRAP_REGSET_H */ |
130 | |