1/*
2 * Copyright (c) 2005-2008 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28/*
29 * @OSF_FREE_COPYRIGHT@
30 */
31/*
32 * @APPLE_FREE_COPYRIGHT@
33 */
34
35/*
36 * Author: Bill Angell, Apple
37 * Date: 10/auht-five
38 *
39 * Random diagnostics, augmented Derek Kumar 2011
40 *
41 *
42 */
43
44
45#include <kern/machine.h>
46#include <kern/processor.h>
47#include <mach/machine.h>
48#include <mach/processor_info.h>
49#include <mach/mach_types.h>
50#include <mach/boolean.h>
51#include <kern/thread.h>
52#include <kern/task.h>
53#include <kern/ipc_kobject.h>
54#include <mach/vm_param.h>
55#include <ipc/port.h>
56#include <ipc/ipc_entry.h>
57#include <ipc/ipc_space.h>
58#include <ipc/ipc_object.h>
59#include <ipc/ipc_port.h>
60#include <vm/vm_kern.h>
61#include <vm/vm_map.h>
62#include <vm/vm_page.h>
63#include <vm/pmap.h>
64#include <pexpert/pexpert.h>
65#include <console/video_console.h>
66#include <i386/cpu_data.h>
67#include <i386/Diagnostics.h>
68#include <i386/mp.h>
69#include <i386/pmCPU.h>
70#include <i386/tsc.h>
71#include <mach/i386/syscall_sw.h>
72#include <kern/kalloc.h>
73#include <sys/kdebug.h>
74#include <i386/machine_cpu.h>
75#include <i386/misc_protos.h>
76#include <i386/cpuid.h>
77
78#if MONOTONIC
79#include <kern/monotonic.h>
80#endif /* MONOTONIC */
81
82#define PERMIT_PERMCHECK (0)
83
84diagWork dgWork;
85uint64_t lastRuptClear = 0ULL;
86boolean_t diag_pmc_enabled = FALSE;
87void cpu_powerstats(void *);
88
89typedef struct {
90 uint64_t caperf;
91 uint64_t cmperf;
92 uint64_t ccres[6];
93 uint64_t crtimes[CPU_RTIME_BINS];
94 uint64_t citimes[CPU_ITIME_BINS];
95 uint64_t crtime_total;
96 uint64_t citime_total;
97 uint64_t cpu_idle_exits;
98 uint64_t cpu_insns;
99 uint64_t cpu_ucc;
100 uint64_t cpu_urc;
101#if DIAG_ALL_PMCS
102 uint64_t gpmcs[4];
103#endif /* DIAG_ALL_PMCS */
104} core_energy_stat_t;
105
106typedef struct {
107 uint64_t pkes_version;
108 uint64_t pkg_cres[2][7];
109 uint64_t pkg_power_unit;
110 uint64_t pkg_energy;
111 uint64_t pp0_energy;
112 uint64_t pp1_energy;
113 uint64_t ddr_energy;
114 uint64_t llc_flushed_cycles;
115 uint64_t ring_ratio_instantaneous;
116 uint64_t IA_frequency_clipping_cause;
117 uint64_t GT_frequency_clipping_cause;
118 uint64_t pkg_idle_exits;
119 uint64_t pkg_rtimes[CPU_RTIME_BINS];
120 uint64_t pkg_itimes[CPU_ITIME_BINS];
121 uint64_t mbus_delay_time;
122 uint64_t mint_delay_time;
123 uint32_t ncpus;
124 core_energy_stat_t cest[];
125} pkg_energy_statistics_t;
126
127
128int
129diagCall64(x86_saved_state_t * state)
130{
131 uint64_t curpos, i, j;
132 uint64_t selector, data;
133 uint64_t currNap, durNap;
134 x86_saved_state64_t *regs;
135 boolean_t diagflag;
136 uint32_t rval = 0;
137
138 assert(is_saved_state64(state));
139 regs = saved_state64(state);
140
141 diagflag = ((dgWork.dgFlags & enaDiagSCs) != 0);
142 selector = regs->rdi;
143
144 switch (selector) { /* Select the routine */
145 case dgRuptStat: /* Suck Interruption statistics */
146 (void) ml_set_interrupts_enabled(TRUE);
147 data = regs->rsi; /* Get the number of processors */
148
149 if (data == 0) { /* If no location is specified for data, clear all
150 * counts
151 */
152 for (i = 0; i < real_ncpus; i++) { /* Cycle through
153 * processors */
154 for (j = 0; j < 256; j++)
155 cpu_data_ptr[i]->cpu_hwIntCnt[j] = 0;
156 }
157
158 lastRuptClear = mach_absolute_time(); /* Get the time of clear */
159 rval = 1; /* Normal return */
160 (void) ml_set_interrupts_enabled(FALSE);
161 break;
162 }
163
164 (void) copyout((char *) &real_ncpus, data, sizeof(real_ncpus)); /* Copy out number of
165 * processors */
166 currNap = mach_absolute_time(); /* Get the time now */
167 durNap = currNap - lastRuptClear; /* Get the last interval
168 * duration */
169 if (durNap == 0)
170 durNap = 1; /* This is a very short time, make it
171 * bigger */
172
173 curpos = data + sizeof(real_ncpus); /* Point to the next
174 * available spot */
175
176 for (i = 0; i < real_ncpus; i++) { /* Move 'em all out */
177 (void) copyout((char *) &durNap, curpos, 8); /* Copy out the time
178 * since last clear */
179 (void) copyout((char *) &cpu_data_ptr[i]->cpu_hwIntCnt, curpos + 8, 256 * sizeof(uint32_t)); /* Copy out interrupt
180 * data for this
181 * processor */
182 curpos = curpos + (256 * sizeof(uint32_t) + 8); /* Point to next out put
183 * slot */
184 }
185 rval = 1;
186 (void) ml_set_interrupts_enabled(FALSE);
187 break;
188
189 case dgPowerStat:
190 {
191 uint32_t c2l = 0, c2h = 0, c3l = 0, c3h = 0, c6l = 0, c6h = 0, c7l = 0, c7h = 0;
192 uint32_t pkg_unit_l = 0, pkg_unit_h = 0, pkg_ecl = 0, pkg_ech = 0;
193
194 pkg_energy_statistics_t pkes;
195 core_energy_stat_t cest;
196
197 bzero(&pkes, sizeof(pkes));
198 bzero(&cest, sizeof(cest));
199
200 pkes.pkes_version = 1ULL;
201 rdmsr_carefully(MSR_IA32_PKG_C2_RESIDENCY, &c2l, &c2h);
202 rdmsr_carefully(MSR_IA32_PKG_C3_RESIDENCY, &c3l, &c3h);
203 rdmsr_carefully(MSR_IA32_PKG_C6_RESIDENCY, &c6l, &c6h);
204 rdmsr_carefully(MSR_IA32_PKG_C7_RESIDENCY, &c7l, &c7h);
205
206 pkes.pkg_cres[0][0] = ((uint64_t)c2h << 32) | c2l;
207 pkes.pkg_cres[0][1] = ((uint64_t)c3h << 32) | c3l;
208 pkes.pkg_cres[0][2] = ((uint64_t)c6h << 32) | c6l;
209 pkes.pkg_cres[0][3] = ((uint64_t)c7h << 32) | c7l;
210
211 uint64_t c8r = ~0ULL, c9r = ~0ULL, c10r = ~0ULL;
212
213 rdmsr64_carefully(MSR_IA32_PKG_C8_RESIDENCY, &c8r);
214 rdmsr64_carefully(MSR_IA32_PKG_C9_RESIDENCY, &c9r);
215 rdmsr64_carefully(MSR_IA32_PKG_C10_RESIDENCY, &c10r);
216
217 pkes.pkg_cres[0][4] = c8r;
218 pkes.pkg_cres[0][5] = c9r;
219 pkes.pkg_cres[0][6] = c10r;
220
221 pkes.ddr_energy = ~0ULL;
222 rdmsr64_carefully(MSR_IA32_DDR_ENERGY_STATUS, &pkes.ddr_energy);
223 pkes.llc_flushed_cycles = ~0ULL;
224 rdmsr64_carefully(MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER, &pkes.llc_flushed_cycles);
225
226 pkes.ring_ratio_instantaneous = ~0ULL;
227 rdmsr64_carefully(MSR_IA32_RING_PERF_STATUS, &pkes.ring_ratio_instantaneous);
228
229 pkes.IA_frequency_clipping_cause = ~0ULL;
230
231 uint32_t ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS;
232 /* Should perhaps be a generic register map module for these
233 * registers with identical functionality that were renumbered.
234 */
235 switch (cpuid_cpufamily()) {
236 case CPUFAMILY_INTEL_SKYLAKE:
237 case CPUFAMILY_INTEL_KABYLAKE:
238 ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS_SKL;
239 break;
240 default:
241 break;
242 }
243
244 rdmsr64_carefully(ia_perf_limits, &pkes.IA_frequency_clipping_cause);
245
246 pkes.GT_frequency_clipping_cause = ~0ULL;
247 rdmsr64_carefully(MSR_IA32_GT_PERF_LIMIT_REASONS, &pkes.GT_frequency_clipping_cause);
248
249 rdmsr_carefully(MSR_IA32_PKG_POWER_SKU_UNIT, &pkg_unit_l, &pkg_unit_h);
250 rdmsr_carefully(MSR_IA32_PKG_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
251 pkes.pkg_power_unit = ((uint64_t)pkg_unit_h << 32) | pkg_unit_l;
252 pkes.pkg_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
253
254 rdmsr_carefully(MSR_IA32_PP0_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
255 pkes.pp0_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
256
257 rdmsr_carefully(MSR_IA32_PP1_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
258 pkes.pp1_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
259
260 pkes.pkg_idle_exits = current_cpu_datap()->lcpu.package->package_idle_exits;
261 pkes.ncpus = real_ncpus;
262
263 (void) ml_set_interrupts_enabled(TRUE);
264
265 copyout(&pkes, regs->rsi, sizeof(pkes));
266 curpos = regs->rsi + sizeof(pkes);
267
268 mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_powerstats, NULL);
269
270 for (i = 0; i < real_ncpus; i++) {
271 (void) ml_set_interrupts_enabled(FALSE);
272
273 cest.caperf = cpu_data_ptr[i]->cpu_aperf;
274 cest.cmperf = cpu_data_ptr[i]->cpu_mperf;
275 cest.ccres[0] = cpu_data_ptr[i]->cpu_c3res;
276 cest.ccres[1] = cpu_data_ptr[i]->cpu_c6res;
277 cest.ccres[2] = cpu_data_ptr[i]->cpu_c7res;
278
279 bcopy(&cpu_data_ptr[i]->cpu_rtimes[0], &cest.crtimes[0], sizeof(cest.crtimes));
280 bcopy(&cpu_data_ptr[i]->cpu_itimes[0], &cest.citimes[0], sizeof(cest.citimes));
281
282 cest.citime_total = cpu_data_ptr[i]->cpu_itime_total;
283 cest.crtime_total = cpu_data_ptr[i]->cpu_rtime_total;
284 cest.cpu_idle_exits = cpu_data_ptr[i]->cpu_idle_exits;
285#if MONOTONIC
286 cest.cpu_insns = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_INSTRS];
287 cest.cpu_ucc = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_CYCLES];
288 cest.cpu_urc = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_REFCYCLES];
289#endif /* MONOTONIC */
290#if DIAG_ALL_PMCS
291 bcopy(&cpu_data_ptr[i]->cpu_gpmcs[0], &cest.gpmcs[0], sizeof(cest.gpmcs));
292#endif /* DIAG_ALL_PMCS */
293 (void) ml_set_interrupts_enabled(TRUE);
294
295 copyout(&cest, curpos, sizeof(cest));
296 curpos += sizeof(cest);
297 }
298 rval = 1;
299 (void) ml_set_interrupts_enabled(FALSE);
300 }
301 break;
302 case dgEnaPMC:
303 {
304 boolean_t enable = TRUE;
305 uint32_t cpuinfo[4];
306 /* Require architectural PMC v2 or higher, corresponding to
307 * Merom+, or equivalent virtualised facility.
308 */
309 do_cpuid(0xA, &cpuinfo[0]);
310 if ((cpuinfo[0] & 0xFF) >= 2) {
311 mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_pmc_control, &enable);
312 diag_pmc_enabled = TRUE;
313 }
314 rval = 1;
315 }
316 break;
317#if DEVELOPMENT || DEBUG
318 case dgGzallocTest:
319 {
320 (void) ml_set_interrupts_enabled(TRUE);
321 if (diagflag) {
322 unsigned *ptr = (unsigned *)kalloc(1024);
323 kfree(ptr, 1024);
324 *ptr = 0x42;
325 }
326 (void) ml_set_interrupts_enabled(FALSE);
327 }
328 break;
329#endif
330
331#if DEVELOPMENT || DEBUG
332 case dgPermCheck:
333 {
334 (void) ml_set_interrupts_enabled(TRUE);
335 if (diagflag)
336 rval = pmap_permissions_verify(kernel_pmap, kernel_map, 0, ~0ULL);
337 (void) ml_set_interrupts_enabled(FALSE);
338 }
339 break;
340#endif /* DEVELOPMENT || DEBUG */
341 default: /* Handle invalid ones */
342 rval = 0; /* Return an exception */
343 }
344
345 regs->rax = rval;
346
347 assert(ml_get_interrupts_enabled() == FALSE);
348 return rval;
349}
350
351void cpu_powerstats(__unused void *arg) {
352 cpu_data_t *cdp = current_cpu_datap();
353 __unused int cnum = cdp->cpu_number;
354 uint32_t cl = 0, ch = 0, mpl = 0, mph = 0, apl = 0, aph = 0;
355
356 rdmsr_carefully(MSR_IA32_MPERF, &mpl, &mph);
357 rdmsr_carefully(MSR_IA32_APERF, &apl, &aph);
358
359 cdp->cpu_mperf = ((uint64_t)mph << 32) | mpl;
360 cdp->cpu_aperf = ((uint64_t)aph << 32) | apl;
361
362 uint64_t ctime = mach_absolute_time();
363 cdp->cpu_rtime_total += ctime - cdp->cpu_ixtime;
364 cdp->cpu_ixtime = ctime;
365
366 rdmsr_carefully(MSR_IA32_CORE_C3_RESIDENCY, &cl, &ch);
367 cdp->cpu_c3res = ((uint64_t)ch << 32) | cl;
368
369 rdmsr_carefully(MSR_IA32_CORE_C6_RESIDENCY, &cl, &ch);
370 cdp->cpu_c6res = ((uint64_t)ch << 32) | cl;
371
372 rdmsr_carefully(MSR_IA32_CORE_C7_RESIDENCY, &cl, &ch);
373 cdp->cpu_c7res = ((uint64_t)ch << 32) | cl;
374
375 if (diag_pmc_enabled) {
376#if MONOTONIC
377 mt_update_fixed_counts();
378#else /* MONOTONIC */
379 uint64_t insns = read_pmc(FIXED_PMC0);
380 uint64_t ucc = read_pmc(FIXED_PMC1);
381 uint64_t urc = read_pmc(FIXED_PMC2);
382#endif /* !MONOTONIC */
383#if DIAG_ALL_PMCS
384 int i;
385
386 for (i = 0; i < 4; i++) {
387 cdp->cpu_gpmcs[i] = read_pmc(i);
388 }
389#endif /* DIAG_ALL_PMCS */
390#if !MONOTONIC
391 cdp->cpu_cur_insns = insns;
392 cdp->cpu_cur_ucc = ucc;
393 cdp->cpu_cur_urc = urc;
394#endif /* !MONOTONIC */
395 }
396}
397
398void cpu_pmc_control(void *enablep) {
399#if !MONOTONIC
400 boolean_t enable = *(boolean_t *)enablep;
401 cpu_data_t *cdp = current_cpu_datap();
402
403 if (enable) {
404 wrmsr64(0x38F, 0x70000000FULL);
405 wrmsr64(0x38D, 0x333);
406 set_cr4(get_cr4() | CR4_PCE);
407
408 } else {
409 wrmsr64(0x38F, 0);
410 wrmsr64(0x38D, 0);
411 set_cr4((get_cr4() & ~CR4_PCE));
412 }
413 cdp->cpu_fixed_pmcs_enabled = enable;
414#else /* !MONOTONIC */
415#pragma unused(enablep)
416#endif /* MONOTONIC */
417}
418