1/*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22
23/*
24 * Copyright (c) 2015, Joyent, Inc.
25 * Copyright (c) 2008 Sun Microsystems, Inc. All rights reserved.
26 */
27
28/*
29 * Copyright (c) 2010, Intel Corporation.
30 * All rights reserved.
31 */
32
33/* Copyright (c) 1988 AT&T */
34/* All Rights Reserved */
35
36/*
37 * APPLE NOTE: There is a copy of this file in userspace in
38 * dtrace:/disassembler/dis_tables.c
39 *
40 * It needs to be in sync with this file.
41 */
42
43/*
44 * #pragma ident "@(#)dis_tables.c 1.18 08/05/24 SMI"
45 */
46#include <sys/dtrace.h>
47#include <sys/dtrace_glue.h>
48#include <sys/dis_tables.h>
49
50/* BEGIN CSTYLED */
51
52/*
53 * Disassembly begins in dis_distable, which is equivalent to the One-byte
54 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The
55 * decoding loops then traverse out through the other tables as necessary to
56 * decode a given instruction.
57 *
58 * The behavior of this file can be controlled by one of the following flags:
59 *
60 * DIS_TEXT Include text for disassembly
61 * DIS_MEM Include memory-size calculations
62 *
63 * Either or both of these can be defined.
64 *
65 * This file is not, and will never be, cstyled. If anything, the tables should
66 * be taken out another tab stop or two so nothing overlaps.
67 */
68
69/*
70 * These functions must be provided for the consumer to do disassembly.
71 */
72#ifdef DIS_TEXT
73extern char *strncpy(char *, const char *, size_t);
74extern size_t strlen(const char *);
75extern int strcmp(const char *, const char *);
76extern int strncmp(const char *, const char *, size_t);
77extern size_t strlcat(char *, const char *, size_t);
78#endif
79
80
81#define TERM 0 /* used to indicate that the 'indirect' */
82 /* field terminates - no pointer. */
83
84/* Used to decode instructions. */
85typedef struct instable {
86 struct instable *it_indirect; /* for decode op codes */
87 uchar_t it_adrmode;
88#ifdef DIS_TEXT
89 char it_name[NCPS];
90 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */
91#endif
92#ifdef DIS_MEM
93 uint_t it_size:16;
94#endif
95 uint_t it_invalid64:1; /* opcode invalid in amd64 */
96 uint_t it_always64:1; /* 64 bit when in 64 bit mode */
97 uint_t it_invalid32:1; /* invalid in IA32 */
98 uint_t it_stackop:1; /* push/pop stack operation */
99 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */
100 uint_t it_avxsuf:1; /* AVX suffix required */
101} instable_t;
102
103/*
104 * Instruction formats.
105 */
106enum {
107 UNKNOWN,
108 MRw,
109 IMlw,
110 IMw,
111 IR,
112 OA,
113 AO,
114 MS,
115 SM,
116 Mv,
117 Mw,
118 M, /* register or memory */
119 MG9, /* register or memory in group 9 (prefix optional) */
120 Mb, /* register or memory, always byte sized */
121 MO, /* memory only (no registers) */
122 PREF,
123 SWAPGS_RDTSCP,
124 MONITOR_MWAIT,
125 R,
126 RA,
127 SEG,
128 MR,
129 RM,
130 RM_66r, /* RM, but with a required 0x66 prefix */
131 IA,
132 MA,
133 SD,
134 ,
135 SA,
136 D,
137 INM,
138 SO,
139 BD,
140 I,
141 P,
142 V,
143 DSHIFT, /* for double shift that has an 8-bit immediate */
144 U,
145 OVERRIDE,
146 NORM, /* instructions w/o ModR/M byte, no memory access */
147 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */
148 O, /* for call */
149 JTAB, /* jump table */
150 IMUL, /* for 186 iimul instr */
151 CBW, /* so data16 can be evaluated for cbw and variants */
152 MvI, /* for 186 logicals */
153 ENTER, /* for 186 enter instr */
154 RMw, /* for 286 arpl instr */
155 Ib, /* for push immediate byte */
156 F, /* for 287 instructions */
157 FF, /* for 287 instructions */
158 FFC, /* for 287 instructions */
159 DM, /* 16-bit data */
160 AM, /* 16-bit addr */
161 LSEG, /* for 3-bit seg reg encoding */
162 MIb, /* for 386 logicals */
163 SREG, /* for 386 special registers */
164 PREFIX, /* a REP instruction prefix */
165 LOCK, /* a LOCK instruction prefix */
166 INT3, /* The int 3 instruction, which has a fake operand */
167 INTx, /* The normal int instruction, with explicit int num */
168 DSHIFTcl, /* for double shift that implicitly uses %cl */
169 CWD, /* so data16 can be evaluated for cwd and variants */
170 RET, /* single immediate 16-bit operand */
171 MOVZ, /* for movs and movz, with different size operands */
172 CRC32, /* for crc32, with different size operands */
173 XADDB, /* for xaddb */
174 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */
175 MOVBE, /* movbe instruction */
176
177/*
178 * MMX/SIMD addressing modes.
179 */
180
181 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */
182 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */
183 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */
184 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */
185 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */
186 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */
187 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */
188 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */
189 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */
190 MMOSH, /* Prefixable MMX mm,imm8 */
191 MM, /* MMX/SIMD-Int mm/mem -> mm */
192 MMS, /* MMX/SIMD-Int mm -> mm/mem */
193 MMSH, /* MMX mm,imm8 */
194 XMMO, /* Prefixable SIMD xmm/mem -> xmm */
195 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */
196 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */
197 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */
198 XMMOX3, /* Prefixable SIMD xmm -> r32 */
199 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */
200 XMMOM, /* Prefixable SIMD xmm -> mem */
201 XMMOMS, /* Prefixable SIMD mem -> xmm */
202 XMM, /* SIMD xmm/mem -> xmm */
203 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */
204 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */
205 XMMXIMPL, /* SIMD xmm -> xmm (mem) */
206 XMM3P, /* SIMD xmm -> r32,imm8 */
207 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */
208 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */
209 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */
210 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */
211 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */
212 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */
213 XMMS, /* SIMD xmm -> xmm/mem */
214 XMMM, /* SIMD mem -> xmm */
215 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */
216 XMMMS, /* SIMD xmm -> mem */
217 XMM3MX, /* SIMD r32/mem -> xmm */
218 XMM3MXS, /* SIMD xmm -> r32/mem */
219 XMMSH, /* SIMD xmm,imm8 */
220 XMMXM3, /* SIMD xmm/mem -> r32 */
221 XMMX3, /* SIMD xmm -> r32 */
222 XMMXMM, /* SIMD xmm/mem -> mm */
223 XMMMX, /* SIMD mm -> xmm */
224 XMMXM, /* SIMD xmm -> mm */
225 XMMX2I, /* SIMD xmm -> xmm, imm, imm */
226 XMM2I, /* SIMD xmm, imm, imm */
227 XMMFENCE, /* SIMD lfence or mfence */
228 XMMSFNC, /* SIMD sfence (none or mem) */
229 XGETBV_XSETBV,
230 VEX_NONE, /* VEX no operand */
231 VEX_MO, /* VEX mod_rm -> implicit reg */
232 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
233 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */
234 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */
235 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */
236 VEX_MX, /* VEX mod_rm -> mod_reg */
237 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */
238 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
239 VEX_MR, /* VEX mod_rm -> mod_reg */
240 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */
241 VEX_RX, /* VEX mod_reg -> mod_rm */
242 VEX_RR, /* VEX mod_rm -> mod_reg */
243 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
244 VEX_RM, /* VEX mod_reg -> mod_rm */
245 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */
246 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
247 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
248 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */
249 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */
250 VMxo, /* VMx instruction with optional prefix */
251 SVM, /* AMD SVM instructions */
252 BLS, /* BLSR, BLSMSK, BLSI */
253 FMA, /* FMA instructions, all VEX_RMrX */
254 ADX /* ADX instructions, support REX.w, mod_rm->mod_reg */
255};
256
257/*
258 * VEX prefixes
259 */
260#define VEX_2bytes 0xC5 /* the first byte of two-byte form */
261#define VEX_3bytes 0xC4 /* the first byte of three-byte form */
262
263#define FILL 0x90 /* Fill byte used for alignment (nop) */
264
265/*
266** Register numbers for the i386
267*/
268#define EAX_REGNO 0
269#define ECX_REGNO 1
270#define EDX_REGNO 2
271#define EBX_REGNO 3
272#define ESP_REGNO 4
273#define EBP_REGNO 5
274#define ESI_REGNO 6
275#define EDI_REGNO 7
276
277/*
278 * modes for immediate values
279 */
280#define MODE_NONE 0
281#define MODE_IPREL 1 /* signed IP relative value */
282#define MODE_SIGNED 2 /* sign extended immediate */
283#define MODE_IMPLIED 3 /* constant value implied from opcode */
284#define MODE_OFFSET 4 /* offset part of an address */
285#define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */
286
287/*
288 * The letters used in these macros are:
289 * IND - indirect to another to another table
290 * "T" - means to Terminate indirections (this is the final opcode)
291 * "S" - means "operand length suffix required"
292 * "Sa" - means AVX2 suffix (d/q) required
293 * "NS" - means "no suffix" which is the operand length suffix of the opcode
294 * "Z" - means instruction size arg required
295 * "u" - means the opcode is invalid in IA32 but valid in amd64
296 * "x" - means the opcode is invalid in amd64, but not IA32
297 * "y" - means the operand size is always 64 bits in 64 bit mode
298 * "p" - means push/pop stack operation
299 * "vr" - means VEX instruction that operates on normal registers, not fpu
300 */
301
302#if defined(DIS_TEXT) && defined(DIS_MEM)
303#define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0, 0, 0}
304#define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0, 0, 0}
305#define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, 0}
306#define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0, 0, 0}
307#define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0, 0, 0}
308#define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0, 0, 0}
309#define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1, 0, 0}
310#define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 0, 0}
311#define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0, 0, 0}
312#define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1, 0}
313#define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0}
314#define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0, 0, 0}
315#define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0, 0, 0}
316#define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1, 0, 0}
317#define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 0}
318#define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1}
319#define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0, 0, 0}
320#define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0, 0, 0}
321#define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0, 0, 0, 0}
322#elif defined(DIS_TEXT)
323#define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0}
324#define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0}
325#define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0}
326#define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0}
327#define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0}
328#define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0}
329#define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1}
330#define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0}
331#define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0}
332#define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1}
333#define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0}
334#define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0}
335#define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0}
336#define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1}
337#define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0}
338#define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1}
339#define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0}
340#define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0}
341#define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
342#elif defined(DIS_MEM)
343#define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0}
344#define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0}
345#define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0}
346#define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0, 0, 0}
347#define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0, 0, 0}
348#define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1, 0, 0}
349#define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0, 0, 0}
350#define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 0}
351#define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0, 0, 0}
352#define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1, 0}
353#define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0}
354#define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0, 0, 0}
355#define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0, 0, 0}
356#define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1, 0, 0}
357#define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 0}
358#define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 1}
359#define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0, 0 ,0}
360#define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0, 0, 0}
361#define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0, 0, 0}
362#else
363#define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0, 0}
364#define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0, 0, 0}
365#define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0}
366#define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0, 0, 0}
367#define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0, 0, 0}
368#define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1, 0, 0}
369#define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0, 0, 0}
370#define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 0}
371#define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0, 0, 0}
372#define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1, 0}
373#define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0}
374#define TSx(name, amode) {TERM, amode, 1, 0, 0, 0, 0, 0}
375#define TSy(name, amode) {TERM, amode, 0, 1, 0, 0, 0, 0}
376#define TSp(name, amode) {TERM, amode, 0, 0, 0, 1, 0, 0}
377#define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 0}
378#define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 1}
379#define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0, 0, 0}
380#define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0, 0, 0}
381#define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0, 0}
382#endif
383
384#ifdef DIS_TEXT
385/*
386 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
387 */
388const char *const dis_addr16[3][8] = {
389"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "",
390 "(%bx)",
391"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)",
392 "(%bx)",
393"(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)",
394 "(%bx)",
395};
396
397
398/*
399 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
400 */
401const char *const dis_addr32_mode0[16] = {
402 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)",
403 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)"
404};
405
406const char *const dis_addr32_mode12[16] = {
407 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)",
408 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)"
409};
410
411/*
412 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
413 */
414const char *const dis_addr64_mode0[16] = {
415 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)",
416 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)"
417};
418const char *const dis_addr64_mode12[16] = {
419 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)",
420 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)"
421};
422
423/*
424 * decode for scale from SIB byte
425 */
426const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" };
427
428/*
429 * decode for scale from VSIB byte, note that we always include the scale factor
430 * to match gas.
431 */
432const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" };
433
434/*
435 * register decoding for normal references to registers (ie. not addressing)
436 */
437const char *const dis_REG8[16] = {
438 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
439 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
440};
441
442const char *const dis_REG8_REX[16] = {
443 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
444 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
445};
446
447const char *const dis_REG16[16] = {
448 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
449 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
450};
451
452const char *const dis_REG32[16] = {
453 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
454 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
455};
456
457const char *const dis_REG64[16] = {
458 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
459 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
460};
461
462const char *const dis_DEBUGREG[16] = {
463 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7",
464 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15"
465};
466
467const char *const dis_CONTROLREG[16] = {
468 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?",
469 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?"
470};
471
472const char *const dis_TESTREG[16] = {
473 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7",
474 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7"
475};
476
477const char *const dis_MMREG[16] = {
478 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7",
479 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
480};
481
482const char *const dis_XMMREG[16] = {
483 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
484 "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15"
485};
486
487const char *const dis_YMMREG[16] = {
488 "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7",
489 "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15"
490};
491
492const char *const dis_SEGREG[16] = {
493 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>",
494 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>"
495};
496
497/*
498 * SIMD predicate suffixes
499 */
500const char *const dis_PREDSUFFIX[8] = {
501 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord"
502};
503
504const char *const dis_AVXvgrp7[3][8] = {
505 /*0 1 2 3 4 5 6 7*/
506/*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""},
507/*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""},
508/*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"}
509};
510
511#endif /* DIS_TEXT */
512
513/*
514 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
515 */
516const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
517
518/*
519 * "decode table" for pause and clflush instructions
520 */
521const instable_t dis_opPause = TNS("pause", NORM);
522
523/*
524 * Decode table for 0x0F00 opcodes
525 */
526const instable_t dis_op0F00[8] = {
527
528/* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M),
529/* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID,
530};
531
532
533/*
534 * Decode table for 0x0F01 opcodes
535 */
536const instable_t dis_op0F01[8] = {
537
538/* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
539/* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP),
540};
541
542/*
543 * Decode table for 0x0F18 opcodes -- SIMD prefetch
544 */
545const instable_t dis_op0F18[8] = {
546
547/* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),
548/* [4] */ INVALID, INVALID, INVALID, INVALID,
549};
550
551/*
552 * Decode table for 0x0FAE opcodes -- SIMD state save/restore
553 */
554const instable_t dis_op0FAE[8] = {
555/* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M),
556/* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
557};
558
559/*
560 * Decode table for 0x0FBA opcodes
561 */
562
563const instable_t dis_op0FBA[8] = {
564
565/* [0] */ INVALID, INVALID, INVALID, INVALID,
566/* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb),
567};
568
569/*
570 * Decode table for 0x0FC7 opcode (group 9)
571 */
572
573const instable_t dis_op0FC7[8] = {
574
575/* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID,
576/* [4] */ INVALID, INVALID, TNS("vmptrld",MG9), TNS("vmptrst",MG9),
577};
578
579/*
580 * Decode table for 0x0FC7 opcode (group 9) mode 3
581 */
582
583const instable_t dis_op0FC7m3[8] = {
584
585/* [0] */ INVALID, INVALID, INVALID, INVALID,
586/* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9),
587};
588
589/*
590 * Decode table for 0x0FC7 opcode with 0x66 prefix
591 */
592
593const instable_t dis_op660FC7[8] = {
594
595/* [0] */ INVALID, INVALID, INVALID, INVALID,
596/* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID,
597};
598
599/*
600 * Decode table for 0x0FC7 opcode with 0xF3 prefix
601 */
602
603const instable_t dis_opF30FC7[8] = {
604
605/* [0] */ INVALID, INVALID, INVALID, INVALID,
606/* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID,
607};
608
609/*
610 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
611 *
612 *bit pattern: 0000 1111 1100 1reg
613 */
614const instable_t dis_op0FC8[4] = {
615/* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID,
616};
617
618/*
619 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
620 */
621const instable_t dis_op0F7123[4][8] = {
622{
623/* [70].0 */ INVALID, INVALID, INVALID, INVALID,
624/* .4 */ INVALID, INVALID, INVALID, INVALID,
625}, {
626/* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID,
627/* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID,
628}, {
629/* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID,
630/* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID,
631}, {
632/* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH),
633/* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH),
634} };
635
636/*
637 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
638 */
639const instable_t dis_opSIMD7123[32] = {
640/* [70].0 */ INVALID, INVALID, INVALID, INVALID,
641/* .4 */ INVALID, INVALID, INVALID, INVALID,
642
643/* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID,
644/* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID,
645
646/* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID,
647/* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID,
648
649/* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH),
650/* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH),
651};
652
653/*
654 * SIMD instructions have been wedged into the existing IA32 instruction
655 * set through the use of prefixes. That is, while 0xf0 0x58 may be
656 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
657 * instruction - addss. At present, three prefixes have been coopted in
658 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The
659 * following tables are used to provide the prefixed instruction names.
660 * The arrays are sparse, but they're fast.
661 */
662
663/*
664 * Decode table for SIMD instructions with the address size (0x66) prefix.
665 */
666const instable_t dis_opSIMDdata16[256] = {
667/* [00] */ INVALID, INVALID, INVALID, INVALID,
668/* [04] */ INVALID, INVALID, INVALID, INVALID,
669/* [08] */ INVALID, INVALID, INVALID, INVALID,
670/* [0C] */ INVALID, INVALID, INVALID, INVALID,
671
672/* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8),
673/* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8),
674/* [18] */ INVALID, INVALID, INVALID, INVALID,
675/* [1C] */ INVALID, INVALID, INVALID, INVALID,
676
677/* [20] */ INVALID, INVALID, INVALID, INVALID,
678/* [24] */ INVALID, INVALID, INVALID, INVALID,
679/* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
680/* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
681
682/* [30] */ INVALID, INVALID, INVALID, INVALID,
683/* [34] */ INVALID, INVALID, INVALID, INVALID,
684/* [38] */ INVALID, INVALID, INVALID, INVALID,
685/* [3C] */ INVALID, INVALID, INVALID, INVALID,
686
687/* [40] */ INVALID, INVALID, INVALID, INVALID,
688/* [44] */ INVALID, INVALID, INVALID, INVALID,
689/* [48] */ INVALID, INVALID, INVALID, INVALID,
690/* [4C] */ INVALID, INVALID, INVALID, INVALID,
691
692/* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID,
693/* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
694/* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
695/* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
696
697/* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
698/* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16),
699/* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
700/* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
701
702/* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID,
703/* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID,
704/* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID,
705/* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16),
706
707/* [80] */ INVALID, INVALID, INVALID, INVALID,
708/* [84] */ INVALID, INVALID, INVALID, INVALID,
709/* [88] */ INVALID, INVALID, INVALID, INVALID,
710/* [8C] */ INVALID, INVALID, INVALID, INVALID,
711
712/* [90] */ INVALID, INVALID, INVALID, INVALID,
713/* [94] */ INVALID, INVALID, INVALID, INVALID,
714/* [98] */ INVALID, INVALID, INVALID, INVALID,
715/* [9C] */ INVALID, INVALID, INVALID, INVALID,
716
717/* [A0] */ INVALID, INVALID, INVALID, INVALID,
718/* [A4] */ INVALID, INVALID, INVALID, INVALID,
719/* [A8] */ INVALID, INVALID, INVALID, INVALID,
720/* [AC] */ INVALID, INVALID, INVALID, INVALID,
721
722/* [B0] */ INVALID, INVALID, INVALID, INVALID,
723/* [B4] */ INVALID, INVALID, INVALID, INVALID,
724/* [B8] */ INVALID, INVALID, INVALID, INVALID,
725/* [BC] */ INVALID, INVALID, INVALID, INVALID,
726
727/* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID,
728/* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID,
729/* [C8] */ INVALID, INVALID, INVALID, INVALID,
730/* [CC] */ INVALID, INVALID, INVALID, INVALID,
731
732/* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16),
733/* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3),
734/* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16),
735/* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16),
736
737/* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16),
738/* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
739/* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16),
740/* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16),
741
742/* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16),
743/* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16),
744/* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16),
745/* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID,
746};
747
748const instable_t dis_opAVX660F[256] = {
749/* [00] */ INVALID, INVALID, INVALID, INVALID,
750/* [04] */ INVALID, INVALID, INVALID, INVALID,
751/* [08] */ INVALID, INVALID, INVALID, INVALID,
752/* [0C] */ INVALID, INVALID, INVALID, INVALID,
753
754/* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8),
755/* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8),
756/* [18] */ INVALID, INVALID, INVALID, INVALID,
757/* [1C] */ INVALID, INVALID, INVALID, INVALID,
758
759/* [20] */ INVALID, INVALID, INVALID, INVALID,
760/* [24] */ INVALID, INVALID, INVALID, INVALID,
761/* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16),
762/* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8),
763
764/* [30] */ INVALID, INVALID, INVALID, INVALID,
765/* [34] */ INVALID, INVALID, INVALID, INVALID,
766/* [38] */ INVALID, INVALID, INVALID, INVALID,
767/* [3C] */ INVALID, INVALID, INVALID, INVALID,
768
769/* [40] */ INVALID, INVALID, INVALID, INVALID,
770/* [44] */ INVALID, INVALID, INVALID, INVALID,
771/* [48] */ INVALID, INVALID, INVALID, INVALID,
772/* [4C] */ INVALID, INVALID, INVALID, INVALID,
773
774/* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID,
775/* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16),
776/* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
777/* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16),
778
779/* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
780/* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16),
781/* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
782/* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
783
784/* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16),
785/* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID,
786/* [78] */ INVALID, INVALID, INVALID, INVALID,
787/* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
788
789/* [80] */ INVALID, INVALID, INVALID, INVALID,
790/* [84] */ INVALID, INVALID, INVALID, INVALID,
791/* [88] */ INVALID, INVALID, INVALID, INVALID,
792/* [8C] */ INVALID, INVALID, INVALID, INVALID,
793
794/* [90] */ INVALID, INVALID, INVALID, INVALID,
795/* [94] */ INVALID, INVALID, INVALID, INVALID,
796/* [98] */ INVALID, INVALID, INVALID, INVALID,
797/* [9C] */ INVALID, INVALID, INVALID, INVALID,
798
799/* [A0] */ INVALID, INVALID, INVALID, INVALID,
800/* [A4] */ INVALID, INVALID, INVALID, INVALID,
801/* [A8] */ INVALID, INVALID, INVALID, INVALID,
802/* [AC] */ INVALID, INVALID, INVALID, INVALID,
803
804/* [B0] */ INVALID, INVALID, INVALID, INVALID,
805/* [B4] */ INVALID, INVALID, INVALID, INVALID,
806/* [B8] */ INVALID, INVALID, INVALID, INVALID,
807/* [BC] */ INVALID, INVALID, INVALID, INVALID,
808
809/* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID,
810/* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID,
811/* [C8] */ INVALID, INVALID, INVALID, INVALID,
812/* [CC] */ INVALID, INVALID, INVALID, INVALID,
813
814/* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16),
815/* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
816/* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16),
817/* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16),
818
819/* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16),
820/* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
821/* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
822/* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
823
824/* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
825/* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
826/* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
827/* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID,
828};
829
830/*
831 * Decode table for SIMD instructions with the repnz (0xf2) prefix.
832 */
833const instable_t dis_opSIMDrepnz[256] = {
834/* [00] */ INVALID, INVALID, INVALID, INVALID,
835/* [04] */ INVALID, INVALID, INVALID, INVALID,
836/* [08] */ INVALID, INVALID, INVALID, INVALID,
837/* [0C] */ INVALID, INVALID, INVALID, INVALID,
838
839/* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID,
840/* [14] */ INVALID, INVALID, INVALID, INVALID,
841/* [18] */ INVALID, INVALID, INVALID, INVALID,
842/* [1C] */ INVALID, INVALID, INVALID, INVALID,
843
844/* [20] */ INVALID, INVALID, INVALID, INVALID,
845/* [24] */ INVALID, INVALID, INVALID, INVALID,
846/* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
847/* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID,
848
849/* [30] */ INVALID, INVALID, INVALID, INVALID,
850/* [34] */ INVALID, INVALID, INVALID, INVALID,
851/* [38] */ INVALID, INVALID, INVALID, INVALID,
852/* [3C] */ INVALID, INVALID, INVALID, INVALID,
853
854/* [40] */ INVALID, INVALID, INVALID, INVALID,
855/* [44] */ INVALID, INVALID, INVALID, INVALID,
856/* [48] */ INVALID, INVALID, INVALID, INVALID,
857/* [4C] */ INVALID, INVALID, INVALID, INVALID,
858
859/* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID,
860/* [54] */ INVALID, INVALID, INVALID, INVALID,
861/* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID,
862/* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8),
863
864/* [60] */ INVALID, INVALID, INVALID, INVALID,
865/* [64] */ INVALID, INVALID, INVALID, INVALID,
866/* [68] */ INVALID, INVALID, INVALID, INVALID,
867/* [6C] */ INVALID, INVALID, INVALID, INVALID,
868
869/* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID,
870/* [74] */ INVALID, INVALID, INVALID, INVALID,
871/* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID,
872/* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID,
873
874/* [80] */ INVALID, INVALID, INVALID, INVALID,
875/* [84] */ INVALID, INVALID, INVALID, INVALID,
876/* [88] */ INVALID, INVALID, INVALID, INVALID,
877/* [0C] */ INVALID, INVALID, INVALID, INVALID,
878
879/* [90] */ INVALID, INVALID, INVALID, INVALID,
880/* [94] */ INVALID, INVALID, INVALID, INVALID,
881/* [98] */ INVALID, INVALID, INVALID, INVALID,
882/* [9C] */ INVALID, INVALID, INVALID, INVALID,
883
884/* [A0] */ INVALID, INVALID, INVALID, INVALID,
885/* [A4] */ INVALID, INVALID, INVALID, INVALID,
886/* [A8] */ INVALID, INVALID, INVALID, INVALID,
887/* [AC] */ INVALID, INVALID, INVALID, INVALID,
888
889/* [B0] */ INVALID, INVALID, INVALID, INVALID,
890/* [B4] */ INVALID, INVALID, INVALID, INVALID,
891/* [B8] */ INVALID, INVALID, INVALID, INVALID,
892/* [BC] */ INVALID, INVALID, INVALID, INVALID,
893
894/* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID,
895/* [C4] */ INVALID, INVALID, INVALID, INVALID,
896/* [C8] */ INVALID, INVALID, INVALID, INVALID,
897/* [CC] */ INVALID, INVALID, INVALID, INVALID,
898
899/* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID,
900/* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID,
901/* [D8] */ INVALID, INVALID, INVALID, INVALID,
902/* [DC] */ INVALID, INVALID, INVALID, INVALID,
903
904/* [E0] */ INVALID, INVALID, INVALID, INVALID,
905/* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID,
906/* [E8] */ INVALID, INVALID, INVALID, INVALID,
907/* [EC] */ INVALID, INVALID, INVALID, INVALID,
908
909/* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID,
910/* [F4] */ INVALID, INVALID, INVALID, INVALID,
911/* [F8] */ INVALID, INVALID, INVALID, INVALID,
912/* [FC] */ INVALID, INVALID, INVALID, INVALID,
913};
914
915const instable_t dis_opAVXF20F[256] = {
916/* [00] */ INVALID, INVALID, INVALID, INVALID,
917/* [04] */ INVALID, INVALID, INVALID, INVALID,
918/* [08] */ INVALID, INVALID, INVALID, INVALID,
919/* [0C] */ INVALID, INVALID, INVALID, INVALID,
920
921/* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID,
922/* [14] */ INVALID, INVALID, INVALID, INVALID,
923/* [18] */ INVALID, INVALID, INVALID, INVALID,
924/* [1C] */ INVALID, INVALID, INVALID, INVALID,
925
926/* [20] */ INVALID, INVALID, INVALID, INVALID,
927/* [24] */ INVALID, INVALID, INVALID, INVALID,
928/* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
929/* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID,
930
931/* [30] */ INVALID, INVALID, INVALID, INVALID,
932/* [34] */ INVALID, INVALID, INVALID, INVALID,
933/* [38] */ INVALID, INVALID, INVALID, INVALID,
934/* [3C] */ INVALID, INVALID, INVALID, INVALID,
935
936/* [40] */ INVALID, INVALID, INVALID, INVALID,
937/* [44] */ INVALID, INVALID, INVALID, INVALID,
938/* [48] */ INVALID, INVALID, INVALID, INVALID,
939/* [4C] */ INVALID, INVALID, INVALID, INVALID,
940
941/* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID,
942/* [54] */ INVALID, INVALID, INVALID, INVALID,
943/* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
944/* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
945
946/* [60] */ INVALID, INVALID, INVALID, INVALID,
947/* [64] */ INVALID, INVALID, INVALID, INVALID,
948/* [68] */ INVALID, INVALID, INVALID, INVALID,
949/* [6C] */ INVALID, INVALID, INVALID, INVALID,
950
951/* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID,
952/* [74] */ INVALID, INVALID, INVALID, INVALID,
953/* [78] */ INVALID, INVALID, INVALID, INVALID,
954/* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID,
955
956/* [80] */ INVALID, INVALID, INVALID, INVALID,
957/* [84] */ INVALID, INVALID, INVALID, INVALID,
958/* [88] */ INVALID, INVALID, INVALID, INVALID,
959/* [0C] */ INVALID, INVALID, INVALID, INVALID,
960
961/* [90] */ INVALID, INVALID, INVALID, INVALID,
962/* [94] */ INVALID, INVALID, INVALID, INVALID,
963/* [98] */ INVALID, INVALID, INVALID, INVALID,
964/* [9C] */ INVALID, INVALID, INVALID, INVALID,
965
966/* [A0] */ INVALID, INVALID, INVALID, INVALID,
967/* [A4] */ INVALID, INVALID, INVALID, INVALID,
968/* [A8] */ INVALID, INVALID, INVALID, INVALID,
969/* [AC] */ INVALID, INVALID, INVALID, INVALID,
970
971/* [B0] */ INVALID, INVALID, INVALID, INVALID,
972/* [B4] */ INVALID, INVALID, INVALID, INVALID,
973/* [B8] */ INVALID, INVALID, INVALID, INVALID,
974/* [BC] */ INVALID, INVALID, INVALID, INVALID,
975
976/* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID,
977/* [C4] */ INVALID, INVALID, INVALID, INVALID,
978/* [C8] */ INVALID, INVALID, INVALID, INVALID,
979/* [CC] */ INVALID, INVALID, INVALID, INVALID,
980
981/* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID,
982/* [D4] */ INVALID, INVALID, INVALID, INVALID,
983/* [D8] */ INVALID, INVALID, INVALID, INVALID,
984/* [DC] */ INVALID, INVALID, INVALID, INVALID,
985
986/* [E0] */ INVALID, INVALID, INVALID, INVALID,
987/* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
988/* [E8] */ INVALID, INVALID, INVALID, INVALID,
989/* [EC] */ INVALID, INVALID, INVALID, INVALID,
990
991/* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID,
992/* [F4] */ INVALID, INVALID, INVALID, INVALID,
993/* [F8] */ INVALID, INVALID, INVALID, INVALID,
994/* [FC] */ INVALID, INVALID, INVALID, INVALID,
995};
996
997const instable_t dis_opAVXF20F3A[256] = {
998/* [00] */ INVALID, INVALID, INVALID, INVALID,
999/* [04] */ INVALID, INVALID, INVALID, INVALID,
1000/* [08] */ INVALID, INVALID, INVALID, INVALID,
1001/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1002
1003/* [10] */ INVALID, INVALID, INVALID, INVALID,
1004/* [14] */ INVALID, INVALID, INVALID, INVALID,
1005/* [18] */ INVALID, INVALID, INVALID, INVALID,
1006/* [1C] */ INVALID, INVALID, INVALID, INVALID,
1007
1008/* [20] */ INVALID, INVALID, INVALID, INVALID,
1009/* [24] */ INVALID, INVALID, INVALID, INVALID,
1010/* [28] */ INVALID, INVALID, INVALID, INVALID,
1011/* [2C] */ INVALID, INVALID, INVALID, INVALID,
1012
1013/* [30] */ INVALID, INVALID, INVALID, INVALID,
1014/* [34] */ INVALID, INVALID, INVALID, INVALID,
1015/* [38] */ INVALID, INVALID, INVALID, INVALID,
1016/* [3C] */ INVALID, INVALID, INVALID, INVALID,
1017
1018/* [40] */ INVALID, INVALID, INVALID, INVALID,
1019/* [44] */ INVALID, INVALID, INVALID, INVALID,
1020/* [48] */ INVALID, INVALID, INVALID, INVALID,
1021/* [4C] */ INVALID, INVALID, INVALID, INVALID,
1022
1023/* [50] */ INVALID, INVALID, INVALID, INVALID,
1024/* [54] */ INVALID, INVALID, INVALID, INVALID,
1025/* [58] */ INVALID, INVALID, INVALID, INVALID,
1026/* [5C] */ INVALID, INVALID, INVALID, INVALID,
1027
1028/* [60] */ INVALID, INVALID, INVALID, INVALID,
1029/* [64] */ INVALID, INVALID, INVALID, INVALID,
1030/* [68] */ INVALID, INVALID, INVALID, INVALID,
1031/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1032
1033/* [70] */ INVALID, INVALID, INVALID, INVALID,
1034/* [74] */ INVALID, INVALID, INVALID, INVALID,
1035/* [78] */ INVALID, INVALID, INVALID, INVALID,
1036/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1037
1038/* [80] */ INVALID, INVALID, INVALID, INVALID,
1039/* [84] */ INVALID, INVALID, INVALID, INVALID,
1040/* [88] */ INVALID, INVALID, INVALID, INVALID,
1041/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1042
1043/* [90] */ INVALID, INVALID, INVALID, INVALID,
1044/* [94] */ INVALID, INVALID, INVALID, INVALID,
1045/* [98] */ INVALID, INVALID, INVALID, INVALID,
1046/* [9C] */ INVALID, INVALID, INVALID, INVALID,
1047
1048/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1049/* [A4] */ INVALID, INVALID, INVALID, INVALID,
1050/* [A8] */ INVALID, INVALID, INVALID, INVALID,
1051/* [AC] */ INVALID, INVALID, INVALID, INVALID,
1052
1053/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1054/* [B4] */ INVALID, INVALID, INVALID, INVALID,
1055/* [B8] */ INVALID, INVALID, INVALID, INVALID,
1056/* [BC] */ INVALID, INVALID, INVALID, INVALID,
1057
1058/* [C0] */ INVALID, INVALID, INVALID, INVALID,
1059/* [C4] */ INVALID, INVALID, INVALID, INVALID,
1060/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1061/* [CC] */ INVALID, INVALID, INVALID, INVALID,
1062
1063/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1064/* [D4] */ INVALID, INVALID, INVALID, INVALID,
1065/* [D8] */ INVALID, INVALID, INVALID, INVALID,
1066/* [DC] */ INVALID, INVALID, INVALID, INVALID,
1067
1068/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1069/* [E4] */ INVALID, INVALID, INVALID, INVALID,
1070/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1071/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1072
1073/* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID,
1074/* [F4] */ INVALID, INVALID, INVALID, INVALID,
1075/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1076/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1077};
1078
1079const instable_t dis_opAVXF20F38[256] = {
1080/* [00] */ INVALID, INVALID, INVALID, INVALID,
1081/* [04] */ INVALID, INVALID, INVALID, INVALID,
1082/* [08] */ INVALID, INVALID, INVALID, INVALID,
1083/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1084
1085/* [10] */ INVALID, INVALID, INVALID, INVALID,
1086/* [14] */ INVALID, INVALID, INVALID, INVALID,
1087/* [18] */ INVALID, INVALID, INVALID, INVALID,
1088/* [1C] */ INVALID, INVALID, INVALID, INVALID,
1089
1090/* [20] */ INVALID, INVALID, INVALID, INVALID,
1091/* [24] */ INVALID, INVALID, INVALID, INVALID,
1092/* [28] */ INVALID, INVALID, INVALID, INVALID,
1093/* [2C] */ INVALID, INVALID, INVALID, INVALID,
1094
1095/* [30] */ INVALID, INVALID, INVALID, INVALID,
1096/* [34] */ INVALID, INVALID, INVALID, INVALID,
1097/* [38] */ INVALID, INVALID, INVALID, INVALID,
1098/* [3C] */ INVALID, INVALID, INVALID, INVALID,
1099
1100/* [40] */ INVALID, INVALID, INVALID, INVALID,
1101/* [44] */ INVALID, INVALID, INVALID, INVALID,
1102/* [48] */ INVALID, INVALID, INVALID, INVALID,
1103/* [4C] */ INVALID, INVALID, INVALID, INVALID,
1104
1105/* [50] */ INVALID, INVALID, INVALID, INVALID,
1106/* [54] */ INVALID, INVALID, INVALID, INVALID,
1107/* [58] */ INVALID, INVALID, INVALID, INVALID,
1108/* [5C] */ INVALID, INVALID, INVALID, INVALID,
1109
1110/* [60] */ INVALID, INVALID, INVALID, INVALID,
1111/* [64] */ INVALID, INVALID, INVALID, INVALID,
1112/* [68] */ INVALID, INVALID, INVALID, INVALID,
1113/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1114
1115/* [70] */ INVALID, INVALID, INVALID, INVALID,
1116/* [74] */ INVALID, INVALID, INVALID, INVALID,
1117/* [78] */ INVALID, INVALID, INVALID, INVALID,
1118/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1119
1120/* [80] */ INVALID, INVALID, INVALID, INVALID,
1121/* [84] */ INVALID, INVALID, INVALID, INVALID,
1122/* [88] */ INVALID, INVALID, INVALID, INVALID,
1123/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1124
1125/* [90] */ INVALID, INVALID, INVALID, INVALID,
1126/* [94] */ INVALID, INVALID, INVALID, INVALID,
1127/* [98] */ INVALID, INVALID, INVALID, INVALID,
1128/* [9C] */ INVALID, INVALID, INVALID, INVALID,
1129
1130/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1131/* [A4] */ INVALID, INVALID, INVALID, INVALID,
1132/* [A8] */ INVALID, INVALID, INVALID, INVALID,
1133/* [AC] */ INVALID, INVALID, INVALID, INVALID,
1134
1135/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1136/* [B4] */ INVALID, INVALID, INVALID, INVALID,
1137/* [B8] */ INVALID, INVALID, INVALID, INVALID,
1138/* [BC] */ INVALID, INVALID, INVALID, INVALID,
1139
1140/* [C0] */ INVALID, INVALID, INVALID, INVALID,
1141/* [C4] */ INVALID, INVALID, INVALID, INVALID,
1142/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1143/* [CC] */ INVALID, INVALID, INVALID, INVALID,
1144
1145/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1146/* [D4] */ INVALID, INVALID, INVALID, INVALID,
1147/* [D8] */ INVALID, INVALID, INVALID, INVALID,
1148/* [DC] */ INVALID, INVALID, INVALID, INVALID,
1149
1150/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1151/* [E4] */ INVALID, INVALID, INVALID, INVALID,
1152/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1153/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1154
1155/* [F0] */ INVALID, INVALID, INVALID, INVALID,
1156/* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
1157/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1158/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1159};
1160
1161const instable_t dis_opAVXF30F38[256] = {
1162/* [00] */ INVALID, INVALID, INVALID, INVALID,
1163/* [04] */ INVALID, INVALID, INVALID, INVALID,
1164/* [08] */ INVALID, INVALID, INVALID, INVALID,
1165/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1166
1167/* [10] */ INVALID, INVALID, INVALID, INVALID,
1168/* [14] */ INVALID, INVALID, INVALID, INVALID,
1169/* [18] */ INVALID, INVALID, INVALID, INVALID,
1170/* [1C] */ INVALID, INVALID, INVALID, INVALID,
1171
1172/* [20] */ INVALID, INVALID, INVALID, INVALID,
1173/* [24] */ INVALID, INVALID, INVALID, INVALID,
1174/* [28] */ INVALID, INVALID, INVALID, INVALID,
1175/* [2C] */ INVALID, INVALID, INVALID, INVALID,
1176
1177/* [30] */ INVALID, INVALID, INVALID, INVALID,
1178/* [34] */ INVALID, INVALID, INVALID, INVALID,
1179/* [38] */ INVALID, INVALID, INVALID, INVALID,
1180/* [3C] */ INVALID, INVALID, INVALID, INVALID,
1181
1182/* [40] */ INVALID, INVALID, INVALID, INVALID,
1183/* [44] */ INVALID, INVALID, INVALID, INVALID,
1184/* [48] */ INVALID, INVALID, INVALID, INVALID,
1185/* [4C] */ INVALID, INVALID, INVALID, INVALID,
1186
1187/* [50] */ INVALID, INVALID, INVALID, INVALID,
1188/* [54] */ INVALID, INVALID, INVALID, INVALID,
1189/* [58] */ INVALID, INVALID, INVALID, INVALID,
1190/* [5C] */ INVALID, INVALID, INVALID, INVALID,
1191
1192/* [60] */ INVALID, INVALID, INVALID, INVALID,
1193/* [64] */ INVALID, INVALID, INVALID, INVALID,
1194/* [68] */ INVALID, INVALID, INVALID, INVALID,
1195/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1196
1197/* [70] */ INVALID, INVALID, INVALID, INVALID,
1198/* [74] */ INVALID, INVALID, INVALID, INVALID,
1199/* [78] */ INVALID, INVALID, INVALID, INVALID,
1200/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1201
1202/* [80] */ INVALID, INVALID, INVALID, INVALID,
1203/* [84] */ INVALID, INVALID, INVALID, INVALID,
1204/* [88] */ INVALID, INVALID, INVALID, INVALID,
1205/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1206
1207/* [90] */ INVALID, INVALID, INVALID, INVALID,
1208/* [94] */ INVALID, INVALID, INVALID, INVALID,
1209/* [98] */ INVALID, INVALID, INVALID, INVALID,
1210/* [9C] */ INVALID, INVALID, INVALID, INVALID,
1211
1212/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1213/* [A4] */ INVALID, INVALID, INVALID, INVALID,
1214/* [A8] */ INVALID, INVALID, INVALID, INVALID,
1215/* [AC] */ INVALID, INVALID, INVALID, INVALID,
1216
1217/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1218/* [B4] */ INVALID, INVALID, INVALID, INVALID,
1219/* [B8] */ INVALID, INVALID, INVALID, INVALID,
1220/* [BC] */ INVALID, INVALID, INVALID, INVALID,
1221
1222/* [C0] */ INVALID, INVALID, INVALID, INVALID,
1223/* [C4] */ INVALID, INVALID, INVALID, INVALID,
1224/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1225/* [CC] */ INVALID, INVALID, INVALID, INVALID,
1226
1227/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1228/* [D4] */ INVALID, INVALID, INVALID, INVALID,
1229/* [D8] */ INVALID, INVALID, INVALID, INVALID,
1230/* [DC] */ INVALID, INVALID, INVALID, INVALID,
1231
1232/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1233/* [E4] */ INVALID, INVALID, INVALID, INVALID,
1234/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1235/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1236
1237/* [F0] */ INVALID, INVALID, INVALID, INVALID,
1238/* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5),
1239/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1240/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1241};
1242/*
1243 * Decode table for SIMD instructions with the repz (0xf3) prefix.
1244 */
1245const instable_t dis_opSIMDrepz[256] = {
1246/* [00] */ INVALID, INVALID, INVALID, INVALID,
1247/* [04] */ INVALID, INVALID, INVALID, INVALID,
1248/* [08] */ INVALID, INVALID, INVALID, INVALID,
1249/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1250
1251/* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID,
1252/* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID,
1253/* [18] */ INVALID, INVALID, INVALID, INVALID,
1254/* [1C] */ INVALID, INVALID, INVALID, INVALID,
1255
1256/* [20] */ INVALID, INVALID, INVALID, INVALID,
1257/* [24] */ INVALID, INVALID, INVALID, INVALID,
1258/* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
1259/* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID,
1260
1261/* [30] */ INVALID, INVALID, INVALID, INVALID,
1262/* [34] */ INVALID, INVALID, INVALID, INVALID,
1263/* [38] */ INVALID, INVALID, INVALID, INVALID,
1264/* [3C] */ INVALID, INVALID, INVALID, INVALID,
1265
1266/* [40] */ INVALID, INVALID, INVALID, INVALID,
1267/* [44] */ INVALID, INVALID, INVALID, INVALID,
1268/* [48] */ INVALID, INVALID, INVALID, INVALID,
1269/* [4C] */ INVALID, INVALID, INVALID, INVALID,
1270
1271/* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4),
1272/* [54] */ INVALID, INVALID, INVALID, INVALID,
1273/* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
1274/* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4),
1275
1276/* [60] */ INVALID, INVALID, INVALID, INVALID,
1277/* [64] */ INVALID, INVALID, INVALID, INVALID,
1278/* [68] */ INVALID, INVALID, INVALID, INVALID,
1279/* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16),
1280
1281/* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID,
1282/* [74] */ INVALID, INVALID, INVALID, INVALID,
1283/* [78] */ INVALID, INVALID, INVALID, INVALID,
1284/* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16),
1285
1286/* [80] */ INVALID, INVALID, INVALID, INVALID,
1287/* [84] */ INVALID, INVALID, INVALID, INVALID,
1288/* [88] */ INVALID, INVALID, INVALID, INVALID,
1289/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1290
1291/* [90] */ INVALID, INVALID, INVALID, INVALID,
1292/* [94] */ INVALID, INVALID, INVALID, INVALID,
1293/* [98] */ INVALID, INVALID, INVALID, INVALID,
1294/* [9C] */ INVALID, INVALID, INVALID, INVALID,
1295
1296/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1297/* [A4] */ INVALID, INVALID, INVALID, INVALID,
1298/* [A8] */ INVALID, INVALID, INVALID, INVALID,
1299/* [AC] */ INVALID, INVALID, INVALID, INVALID,
1300
1301/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1302/* [B4] */ INVALID, INVALID, INVALID, INVALID,
1303/* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID,
1304/* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID,
1305
1306/* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID,
1307/* [C4] */ INVALID, INVALID, INVALID, INVALID,
1308/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1309/* [CC] */ INVALID, INVALID, INVALID, INVALID,
1310
1311/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1312/* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID,
1313/* [D8] */ INVALID, INVALID, INVALID, INVALID,
1314/* [DC] */ INVALID, INVALID, INVALID, INVALID,
1315
1316/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1317/* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID,
1318/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1319/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1320
1321/* [F0] */ INVALID, INVALID, INVALID, INVALID,
1322/* [F4] */ INVALID, INVALID, INVALID, INVALID,
1323/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1324/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1325};
1326
1327const instable_t dis_opAVXF30F[256] = {
1328/* [00] */ INVALID, INVALID, INVALID, INVALID,
1329/* [04] */ INVALID, INVALID, INVALID, INVALID,
1330/* [08] */ INVALID, INVALID, INVALID, INVALID,
1331/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1332
1333/* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID,
1334/* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID,
1335/* [18] */ INVALID, INVALID, INVALID, INVALID,
1336/* [1C] */ INVALID, INVALID, INVALID, INVALID,
1337
1338/* [20] */ INVALID, INVALID, INVALID, INVALID,
1339/* [24] */ INVALID, INVALID, INVALID, INVALID,
1340/* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID,
1341/* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID,
1342
1343/* [30] */ INVALID, INVALID, INVALID, INVALID,
1344/* [34] */ INVALID, INVALID, INVALID, INVALID,
1345/* [38] */ INVALID, INVALID, INVALID, INVALID,
1346/* [3C] */ INVALID, INVALID, INVALID, INVALID,
1347
1348/* [40] */ INVALID, INVALID, INVALID, INVALID,
1349/* [44] */ INVALID, INVALID, INVALID, INVALID,
1350/* [48] */ INVALID, INVALID, INVALID, INVALID,
1351/* [4C] */ INVALID, INVALID, INVALID, INVALID,
1352
1353/* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4),
1354/* [54] */ INVALID, INVALID, INVALID, INVALID,
1355/* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16),
1356/* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4),
1357
1358/* [60] */ INVALID, INVALID, INVALID, INVALID,
1359/* [64] */ INVALID, INVALID, INVALID, INVALID,
1360/* [68] */ INVALID, INVALID, INVALID, INVALID,
1361/* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16),
1362
1363/* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID,
1364/* [74] */ INVALID, INVALID, INVALID, INVALID,
1365/* [78] */ INVALID, INVALID, INVALID, INVALID,
1366/* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16),
1367
1368/* [80] */ INVALID, INVALID, INVALID, INVALID,
1369/* [84] */ INVALID, INVALID, INVALID, INVALID,
1370/* [88] */ INVALID, INVALID, INVALID, INVALID,
1371/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1372
1373/* [90] */ INVALID, INVALID, INVALID, INVALID,
1374/* [94] */ INVALID, INVALID, INVALID, INVALID,
1375/* [98] */ INVALID, INVALID, INVALID, INVALID,
1376/* [9C] */ INVALID, INVALID, INVALID, INVALID,
1377
1378/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1379/* [A4] */ INVALID, INVALID, INVALID, INVALID,
1380/* [A8] */ INVALID, INVALID, INVALID, INVALID,
1381/* [AC] */ INVALID, INVALID, INVALID, INVALID,
1382
1383/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1384/* [B4] */ INVALID, INVALID, INVALID, INVALID,
1385/* [B8] */ INVALID, INVALID, INVALID, INVALID,
1386/* [BC] */ INVALID, INVALID, INVALID, INVALID,
1387
1388/* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID,
1389/* [C4] */ INVALID, INVALID, INVALID, INVALID,
1390/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1391/* [CC] */ INVALID, INVALID, INVALID, INVALID,
1392
1393/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1394/* [D4] */ INVALID, INVALID, INVALID, INVALID,
1395/* [D8] */ INVALID, INVALID, INVALID, INVALID,
1396/* [DC] */ INVALID, INVALID, INVALID, INVALID,
1397
1398/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1399/* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID,
1400/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1401/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1402
1403/* [F0] */ INVALID, INVALID, INVALID, INVALID,
1404/* [F4] */ INVALID, INVALID, INVALID, INVALID,
1405/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1406/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1407};
1408/*
1409 * The following two tables are used to encode crc32 and movbe
1410 * since they share the same opcodes.
1411 */
1412const instable_t dis_op0F38F0[2] = {
1413/* [00] */ TNS("crc32b",CRC32),
1414 TS("movbe",MOVBE),
1415};
1416
1417const instable_t dis_op0F38F1[2] = {
1418/* [00] */ TS("crc32",CRC32),
1419 TS("movbe",MOVBE),
1420};
1421
1422/*
1423 * The following table is used to distinguish between adox and adcx which share
1424 * the same opcodes.
1425 */
1426const instable_t dis_op0F38F6[2] = {
1427/* [00] */ TNS("adcx",ADX),
1428 TNS("adox",ADX),
1429};
1430
1431const instable_t dis_op0F38[256] = {
1432/* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
1433/* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
1434/* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
1435/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1436
1437/* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID,
1438/* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16),
1439/* [18] */ INVALID, INVALID, INVALID, INVALID,
1440/* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID,
1441
1442/* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
1443/* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID,
1444/* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
1445/* [2C] */ INVALID, INVALID, INVALID, INVALID,
1446
1447/* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
1448/* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16),
1449/* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
1450/* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
1451
1452/* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID,
1453/* [44] */ INVALID, INVALID, INVALID, INVALID,
1454/* [48] */ INVALID, INVALID, INVALID, INVALID,
1455/* [4C] */ INVALID, INVALID, INVALID, INVALID,
1456
1457/* [50] */ INVALID, INVALID, INVALID, INVALID,
1458/* [54] */ INVALID, INVALID, INVALID, INVALID,
1459/* [58] */ INVALID, INVALID, INVALID, INVALID,
1460/* [5C] */ INVALID, INVALID, INVALID, INVALID,
1461
1462/* [60] */ INVALID, INVALID, INVALID, INVALID,
1463/* [64] */ INVALID, INVALID, INVALID, INVALID,
1464/* [68] */ INVALID, INVALID, INVALID, INVALID,
1465/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1466
1467/* [70] */ INVALID, INVALID, INVALID, INVALID,
1468/* [74] */ INVALID, INVALID, INVALID, INVALID,
1469/* [78] */ INVALID, INVALID, INVALID, INVALID,
1470/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1471
1472/* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID,
1473/* [84] */ INVALID, INVALID, INVALID, INVALID,
1474/* [88] */ INVALID, INVALID, INVALID, INVALID,
1475/* [8C] */ INVALID, INVALID, INVALID, INVALID,
1476
1477/* [90] */ INVALID, INVALID, INVALID, INVALID,
1478/* [94] */ INVALID, INVALID, INVALID, INVALID,
1479/* [98] */ INVALID, INVALID, INVALID, INVALID,
1480/* [9C] */ INVALID, INVALID, INVALID, INVALID,
1481
1482/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1483/* [A4] */ INVALID, INVALID, INVALID, INVALID,
1484/* [A8] */ INVALID, INVALID, INVALID, INVALID,
1485/* [AC] */ INVALID, INVALID, INVALID, INVALID,
1486
1487/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1488/* [B4] */ INVALID, INVALID, INVALID, INVALID,
1489/* [B8] */ INVALID, INVALID, INVALID, INVALID,
1490/* [BC] */ INVALID, INVALID, INVALID, INVALID,
1491
1492/* [C0] */ INVALID, INVALID, INVALID, INVALID,
1493/* [C4] */ INVALID, INVALID, INVALID, INVALID,
1494/* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16),
1495/* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, INVALID,
1496
1497/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1498/* [D4] */ INVALID, INVALID, INVALID, INVALID,
1499/* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16),
1500/* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
1501
1502/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1503/* [E4] */ INVALID, INVALID, INVALID, INVALID,
1504/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1505/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1506/* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
1507/* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID,
1508/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1509/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1510};
1511
1512const instable_t dis_opAVX660F38[256] = {
1513/* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1514/* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1515/* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1516/* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
1517
1518/* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16),
1519/* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16),
1520/* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1521/* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID,
1522
1523/* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1524/* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID,
1525/* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1526/* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
1527
1528/* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
1529/* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
1530/* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
1531/* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
1532
1533/* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID,
1534/* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
1535/* [48] */ INVALID, INVALID, INVALID, INVALID,
1536/* [4C] */ INVALID, INVALID, INVALID, INVALID,
1537
1538/* [50] */ INVALID, INVALID, INVALID, INVALID,
1539/* [54] */ INVALID, INVALID, INVALID, INVALID,
1540/* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
1541/* [5C] */ INVALID, INVALID, INVALID, INVALID,
1542
1543/* [60] */ INVALID, INVALID, INVALID, INVALID,
1544/* [64] */ INVALID, INVALID, INVALID, INVALID,
1545/* [68] */ INVALID, INVALID, INVALID, INVALID,
1546/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1547
1548/* [70] */ INVALID, INVALID, INVALID, INVALID,
1549/* [74] */ INVALID, INVALID, INVALID, INVALID,
1550/* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID,
1551/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1552
1553/* [80] */ INVALID, INVALID, INVALID, INVALID,
1554/* [84] */ INVALID, INVALID, INVALID, INVALID,
1555/* [88] */ INVALID, INVALID, INVALID, INVALID,
1556/* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID,
1557
1558/* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
1559/* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16),
1560/* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
1561/* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
1562
1563/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1564/* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16),
1565/* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
1566/* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
1567
1568/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1569/* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16),
1570/* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
1571/* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
1572
1573/* [C0] */ INVALID, INVALID, INVALID, INVALID,
1574/* [C4] */ INVALID, INVALID, INVALID, INVALID,
1575/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1576/* [CC] */ INVALID, INVALID, INVALID, INVALID,
1577
1578/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1579/* [D4] */ INVALID, INVALID, INVALID, INVALID,
1580/* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16),
1581/* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
1582
1583/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1584/* [E4] */ INVALID, INVALID, INVALID, INVALID,
1585/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1586/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1587/* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID,
1588/* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5),
1589/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1590/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1591};
1592
1593const instable_t dis_op0F3A[256] = {
1594/* [00] */ INVALID, INVALID, INVALID, INVALID,
1595/* [04] */ INVALID, INVALID, INVALID, INVALID,
1596/* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
1597/* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
1598
1599/* [10] */ INVALID, INVALID, INVALID, INVALID,
1600/* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
1601/* [18] */ INVALID, INVALID, INVALID, INVALID,
1602/* [1C] */ INVALID, INVALID, INVALID, INVALID,
1603
1604/* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
1605/* [24] */ INVALID, INVALID, INVALID, INVALID,
1606/* [28] */ INVALID, INVALID, INVALID, INVALID,
1607/* [2C] */ INVALID, INVALID, INVALID, INVALID,
1608
1609/* [30] */ INVALID, INVALID, INVALID, INVALID,
1610/* [34] */ INVALID, INVALID, INVALID, INVALID,
1611/* [38] */ INVALID, INVALID, INVALID, INVALID,
1612/* [3C] */ INVALID, INVALID, INVALID, INVALID,
1613
1614/* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
1615/* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID,
1616/* [48] */ INVALID, INVALID, INVALID, INVALID,
1617/* [4C] */ INVALID, INVALID, INVALID, INVALID,
1618
1619/* [50] */ INVALID, INVALID, INVALID, INVALID,
1620/* [54] */ INVALID, INVALID, INVALID, INVALID,
1621/* [58] */ INVALID, INVALID, INVALID, INVALID,
1622/* [5C] */ INVALID, INVALID, INVALID, INVALID,
1623
1624/* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
1625/* [64] */ INVALID, INVALID, INVALID, INVALID,
1626/* [68] */ INVALID, INVALID, INVALID, INVALID,
1627/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1628
1629/* [70] */ INVALID, INVALID, INVALID, INVALID,
1630/* [74] */ INVALID, INVALID, INVALID, INVALID,
1631/* [78] */ INVALID, INVALID, INVALID, INVALID,
1632/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1633
1634/* [80] */ INVALID, INVALID, INVALID, INVALID,
1635/* [84] */ INVALID, INVALID, INVALID, INVALID,
1636/* [88] */ INVALID, INVALID, INVALID, INVALID,
1637/* [8C] */ INVALID, INVALID, INVALID, INVALID,
1638
1639/* [90] */ INVALID, INVALID, INVALID, INVALID,
1640/* [94] */ INVALID, INVALID, INVALID, INVALID,
1641/* [98] */ INVALID, INVALID, INVALID, INVALID,
1642/* [9C] */ INVALID, INVALID, INVALID, INVALID,
1643
1644/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1645/* [A4] */ INVALID, INVALID, INVALID, INVALID,
1646/* [A8] */ INVALID, INVALID, INVALID, INVALID,
1647/* [AC] */ INVALID, INVALID, INVALID, INVALID,
1648
1649/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1650/* [B4] */ INVALID, INVALID, INVALID, INVALID,
1651/* [B8] */ INVALID, INVALID, INVALID, INVALID,
1652/* [BC] */ INVALID, INVALID, INVALID, INVALID,
1653
1654/* [C0] */ INVALID, INVALID, INVALID, INVALID,
1655/* [C4] */ INVALID, INVALID, INVALID, INVALID,
1656/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1657/* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, INVALID, INVALID,
1658
1659/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1660/* [D4] */ INVALID, INVALID, INVALID, INVALID,
1661/* [D8] */ INVALID, INVALID, INVALID, INVALID,
1662/* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16),
1663
1664/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1665/* [E4] */ INVALID, INVALID, INVALID, INVALID,
1666/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1667/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1668
1669/* [F0] */ INVALID, INVALID, INVALID, INVALID,
1670/* [F4] */ INVALID, INVALID, INVALID, INVALID,
1671/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1672/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1673};
1674
1675const instable_t dis_opAVX660F3A[256] = {
1676/* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
1677/* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1678/* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1679/* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1680
1681/* [10] */ INVALID, INVALID, INVALID, INVALID,
1682/* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1683/* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID,
1684/* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID,
1685
1686/* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1687/* [24] */ INVALID, INVALID, INVALID, INVALID,
1688/* [28] */ INVALID, INVALID, INVALID, INVALID,
1689/* [2C] */ INVALID, INVALID, INVALID, INVALID,
1690
1691/* [30] */ INVALID, INVALID, INVALID, INVALID,
1692/* [34] */ INVALID, INVALID, INVALID, INVALID,
1693/* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID,
1694/* [3C] */ INVALID, INVALID, INVALID, INVALID,
1695
1696/* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
1697/* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID,
1698/* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16),
1699/* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID,
1700
1701/* [50] */ INVALID, INVALID, INVALID, INVALID,
1702/* [54] */ INVALID, INVALID, INVALID, INVALID,
1703/* [58] */ INVALID, INVALID, INVALID, INVALID,
1704/* [5C] */ INVALID, INVALID, INVALID, INVALID,
1705
1706/* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
1707/* [64] */ INVALID, INVALID, INVALID, INVALID,
1708/* [68] */ INVALID, INVALID, INVALID, INVALID,
1709/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1710
1711/* [70] */ INVALID, INVALID, INVALID, INVALID,
1712/* [74] */ INVALID, INVALID, INVALID, INVALID,
1713/* [78] */ INVALID, INVALID, INVALID, INVALID,
1714/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1715
1716/* [80] */ INVALID, INVALID, INVALID, INVALID,
1717/* [84] */ INVALID, INVALID, INVALID, INVALID,
1718/* [88] */ INVALID, INVALID, INVALID, INVALID,
1719/* [8C] */ INVALID, INVALID, INVALID, INVALID,
1720
1721/* [90] */ INVALID, INVALID, INVALID, INVALID,
1722/* [94] */ INVALID, INVALID, INVALID, INVALID,
1723/* [98] */ INVALID, INVALID, INVALID, INVALID,
1724/* [9C] */ INVALID, INVALID, INVALID, INVALID,
1725
1726/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1727/* [A4] */ INVALID, INVALID, INVALID, INVALID,
1728/* [A8] */ INVALID, INVALID, INVALID, INVALID,
1729/* [AC] */ INVALID, INVALID, INVALID, INVALID,
1730
1731/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1732/* [B4] */ INVALID, INVALID, INVALID, INVALID,
1733/* [B8] */ INVALID, INVALID, INVALID, INVALID,
1734/* [BC] */ INVALID, INVALID, INVALID, INVALID,
1735
1736/* [C0] */ INVALID, INVALID, INVALID, INVALID,
1737/* [C4] */ INVALID, INVALID, INVALID, INVALID,
1738/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1739/* [CC] */ INVALID, INVALID, INVALID, INVALID,
1740
1741/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1742/* [D4] */ INVALID, INVALID, INVALID, INVALID,
1743/* [D8] */ INVALID, INVALID, INVALID, INVALID,
1744/* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16),
1745
1746/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1747/* [E4] */ INVALID, INVALID, INVALID, INVALID,
1748/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1749/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1750
1751/* [F0] */ INVALID, INVALID, INVALID, INVALID,
1752/* [F4] */ INVALID, INVALID, INVALID, INVALID,
1753/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1754/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1755};
1756
1757/*
1758 * Decode table for 0x0F0D which uses the first byte of the mod_rm to
1759 * indicate a sub-code.
1760 */
1761const instable_t dis_op0F0D[8] = {
1762/* [00] */ INVALID, TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID,
1763/* [04] */ INVALID, INVALID, INVALID, INVALID,
1764};
1765
1766/*
1767 * Decode table for 0x0F opcodes
1768 */
1769
1770const instable_t dis_op0F[16][16] = {
1771{
1772/* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR),
1773/* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM),
1774/* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM),
1775/* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID,
1776}, {
1777/* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
1778/* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1779/* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID,
1780/* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw),
1781}, {
1782/* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG),
1783/* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID,
1784/* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1785/* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1786}, {
1787/* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM),
1788/* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID,
1789/* [38] */ INVALID, INVALID, INVALID, INVALID,
1790/* [3C] */ INVALID, INVALID, INVALID, INVALID,
1791}, {
1792/* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR),
1793/* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR),
1794/* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR),
1795/* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR),
1796}, {
1797/* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
1798/* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16),
1799/* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
1800/* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16),
1801}, {
1802/* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1803/* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
1804/* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1805/* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
1806}, {
1807/* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR),
1808/* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
1809/* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID,
1810/* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8),
1811}, {
1812/* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D),
1813/* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D),
1814/* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D),
1815/* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D),
1816}, {
1817/* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb),
1818/* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb),
1819/* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb),
1820/* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb),
1821}, {
1822/* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw),
1823/* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID,
1824/* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw),
1825/* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw),
1826}, {
1827/* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw),
1828/* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ),
1829/* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw),
1830/* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ),
1831}, {
1832/* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM),
1833/* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
1834/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1835/* [CC] */ INVALID, INVALID, INVALID, INVALID,
1836}, {
1837/* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8),
1838/* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3),
1839/* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8),
1840/* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8),
1841}, {
1842/* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8),
1843/* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8),
1844/* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8),
1845/* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8),
1846}, {
1847/* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8),
1848/* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8),
1849/* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8),
1850/* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID,
1851} };
1852
1853const instable_t dis_opAVX0F[16][16] = {
1854{
1855/* [00] */ INVALID, INVALID, INVALID, INVALID,
1856/* [04] */ INVALID, INVALID, INVALID, INVALID,
1857/* [08] */ INVALID, INVALID, INVALID, INVALID,
1858/* [0C] */ INVALID, INVALID, INVALID, INVALID,
1859}, {
1860/* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8),
1861/* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
1862/* [18] */ INVALID, INVALID, INVALID, INVALID,
1863/* [1C] */ INVALID, INVALID, INVALID, INVALID,
1864}, {
1865/* [20] */ INVALID, INVALID, INVALID, INVALID,
1866/* [24] */ INVALID, INVALID, INVALID, INVALID,
1867/* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16),
1868/* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4),
1869}, {
1870/* [30] */ INVALID, INVALID, INVALID, INVALID,
1871/* [34] */ INVALID, INVALID, INVALID, INVALID,
1872/* [38] */ INVALID, INVALID, INVALID, INVALID,
1873/* [3C] */ INVALID, INVALID, INVALID, INVALID,
1874}, {
1875/* [40] */ INVALID, INVALID, INVALID, INVALID,
1876/* [44] */ INVALID, INVALID, INVALID, INVALID,
1877/* [48] */ INVALID, INVALID, INVALID, INVALID,
1878/* [4C] */ INVALID, INVALID, INVALID, INVALID,
1879}, {
1880/* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
1881/* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16),
1882/* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
1883/* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16),
1884}, {
1885/* [60] */ INVALID, INVALID, INVALID, INVALID,
1886/* [64] */ INVALID, INVALID, INVALID, INVALID,
1887/* [68] */ INVALID, INVALID, INVALID, INVALID,
1888/* [6C] */ INVALID, INVALID, INVALID, INVALID,
1889}, {
1890/* [70] */ INVALID, INVALID, INVALID, INVALID,
1891/* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE),
1892/* [78] */ INVALID, INVALID, INVALID, INVALID,
1893/* [7C] */ INVALID, INVALID, INVALID, INVALID,
1894}, {
1895/* [80] */ INVALID, INVALID, INVALID, INVALID,
1896/* [84] */ INVALID, INVALID, INVALID, INVALID,
1897/* [88] */ INVALID, INVALID, INVALID, INVALID,
1898/* [8C] */ INVALID, INVALID, INVALID, INVALID,
1899}, {
1900/* [90] */ INVALID, INVALID, INVALID, INVALID,
1901/* [94] */ INVALID, INVALID, INVALID, INVALID,
1902/* [98] */ INVALID, INVALID, INVALID, INVALID,
1903/* [9C] */ INVALID, INVALID, INVALID, INVALID,
1904}, {
1905/* [A0] */ INVALID, INVALID, INVALID, INVALID,
1906/* [A4] */ INVALID, INVALID, INVALID, INVALID,
1907/* [A8] */ INVALID, INVALID, INVALID, INVALID,
1908/* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID,
1909}, {
1910/* [B0] */ INVALID, INVALID, INVALID, INVALID,
1911/* [B4] */ INVALID, INVALID, INVALID, INVALID,
1912/* [B8] */ INVALID, INVALID, INVALID, INVALID,
1913/* [BC] */ INVALID, INVALID, INVALID, INVALID,
1914}, {
1915/* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID,
1916/* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID,
1917/* [C8] */ INVALID, INVALID, INVALID, INVALID,
1918/* [CC] */ INVALID, INVALID, INVALID, INVALID,
1919}, {
1920/* [D0] */ INVALID, INVALID, INVALID, INVALID,
1921/* [D4] */ INVALID, INVALID, INVALID, INVALID,
1922/* [D8] */ INVALID, INVALID, INVALID, INVALID,
1923/* [DC] */ INVALID, INVALID, INVALID, INVALID,
1924}, {
1925/* [E0] */ INVALID, INVALID, INVALID, INVALID,
1926/* [E4] */ INVALID, INVALID, INVALID, INVALID,
1927/* [E8] */ INVALID, INVALID, INVALID, INVALID,
1928/* [EC] */ INVALID, INVALID, INVALID, INVALID,
1929}, {
1930/* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5),
1931/* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5),
1932/* [F8] */ INVALID, INVALID, INVALID, INVALID,
1933/* [FC] */ INVALID, INVALID, INVALID, INVALID,
1934} };
1935
1936/*
1937 * Decode table for 0x80 opcodes
1938 */
1939
1940const instable_t dis_op80[8] = {
1941
1942/* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw),
1943/* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw),
1944};
1945
1946
1947/*
1948 * Decode table for 0x81 opcodes.
1949 */
1950
1951const instable_t dis_op81[8] = {
1952
1953/* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw),
1954/* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw),
1955};
1956
1957
1958/*
1959 * Decode table for 0x82 opcodes.
1960 */
1961
1962const instable_t dis_op82[8] = {
1963
1964/* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw),
1965/* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw),
1966};
1967/*
1968 * Decode table for 0x83 opcodes.
1969 */
1970
1971const instable_t dis_op83[8] = {
1972
1973/* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw),
1974/* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw),
1975};
1976
1977/*
1978 * Decode table for 0xC0 opcodes.
1979 */
1980
1981const instable_t dis_opC0[8] = {
1982
1983/* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI),
1984/* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI),
1985};
1986
1987/*
1988 * Decode table for 0xD0 opcodes.
1989 */
1990
1991const instable_t dis_opD0[8] = {
1992
1993/* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
1994/* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
1995};
1996
1997/*
1998 * Decode table for 0xC1 opcodes.
1999 * 186 instruction set
2000 */
2001
2002const instable_t dis_opC1[8] = {
2003
2004/* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI),
2005/* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI),
2006};
2007
2008/*
2009 * Decode table for 0xD1 opcodes.
2010 */
2011
2012const instable_t dis_opD1[8] = {
2013
2014/* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
2015/* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv),
2016};
2017
2018
2019/*
2020 * Decode table for 0xD2 opcodes.
2021 */
2022
2023const instable_t dis_opD2[8] = {
2024
2025/* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv),
2026/* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv),
2027};
2028/*
2029 * Decode table for 0xD3 opcodes.
2030 */
2031
2032const instable_t dis_opD3[8] = {
2033
2034/* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv),
2035/* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv),
2036};
2037
2038
2039/*
2040 * Decode table for 0xF6 opcodes.
2041 */
2042
2043const instable_t dis_opF6[8] = {
2044
2045/* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw),
2046/* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA),
2047};
2048
2049
2050/*
2051 * Decode table for 0xF7 opcodes.
2052 */
2053
2054const instable_t dis_opF7[8] = {
2055
2056/* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw),
2057/* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA),
2058};
2059
2060
2061/*
2062 * Decode table for 0xFE opcodes.
2063 */
2064
2065const instable_t dis_opFE[8] = {
2066
2067/* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID,
2068/* [4] */ INVALID, INVALID, INVALID, INVALID,
2069};
2070/*
2071 * Decode table for 0xFF opcodes.
2072 */
2073
2074const instable_t dis_opFF[8] = {
2075
2076/* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM),
2077/* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID,
2078};
2079
2080/* for 287 instructions, which are a mess to decode */
2081
2082const instable_t dis_opFP1n2[8][8] = {
2083{
2084/* bit pattern: 1101 1xxx MODxx xR/M */
2085/* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M),
2086/* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M),
2087}, {
2088/* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M),
2089/* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2),
2090}, {
2091/* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M),
2092/* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M),
2093}, {
2094/* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M),
2095/* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10),
2096}, {
2097/* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8),
2098/* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8),
2099}, {
2100/* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8),
2101/* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2),
2102}, {
2103/* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2),
2104/* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2),
2105}, {
2106/* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2),
2107/* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8),
2108} };
2109
2110const instable_t dis_opFP3[8][8] = {
2111{
2112/* bit pattern: 1101 1xxx 11xx xREG */
2113/* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
2114/* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
2115}, {
2116/* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F),
2117/* [1,4] */ INVALID, INVALID, INVALID, INVALID,
2118}, {
2119/* [2,0] */ INVALID, INVALID, INVALID, INVALID,
2120/* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID,
2121}, {
2122/* [3,0] */ INVALID, INVALID, INVALID, INVALID,
2123/* [3,4] */ INVALID, INVALID, INVALID, INVALID,
2124}, {
2125/* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F),
2126/* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF),
2127}, {
2128/* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F),
2129/* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID,
2130}, {
2131/* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM),
2132/* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF),
2133}, {
2134/* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F),
2135/* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID,
2136} };
2137
2138const instable_t dis_opFP4[4][8] = {
2139{
2140/* bit pattern: 1101 1001 111x xxxx */
2141/* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID,
2142/* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID,
2143}, {
2144/* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM),
2145/* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID,
2146}, {
2147/* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM),
2148/* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM),
2149}, {
2150/* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM),
2151/* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM),
2152} };
2153
2154const instable_t dis_opFP5[8] = {
2155/* bit pattern: 1101 1011 111x xxxx */
2156/* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM),
2157/* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID,
2158};
2159
2160const instable_t dis_opFP6[8] = {
2161/* bit pattern: 1101 1011 11yy yxxx */
2162/* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF),
2163/* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID,
2164};
2165
2166const instable_t dis_opFP7[8] = {
2167/* bit pattern: 1101 1010 11yy yxxx */
2168/* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF),
2169/* [04] */ INVALID, INVALID, INVALID, INVALID,
2170};
2171
2172/*
2173 * Main decode table for the op codes. The first two nibbles
2174 * will be used as an index into the table. If there is a
2175 * a need to further decode an instruction, the array to be
2176 * referenced is indicated with the other two entries being
2177 * empty.
2178 */
2179
2180const instable_t dis_distable[16][16] = {
2181{
2182/* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw),
2183/* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG),
2184/* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw),
2185/* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F),
2186}, {
2187/* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw),
2188/* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG),
2189/* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw),
2190/* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG),
2191}, {
2192/* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw),
2193/* [2,4] */ TNS("andb",IA), TS("and",IA), TNS("%es:",OVERRIDE), TNSx("daa",NORM),
2194/* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw),
2195/* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM),
2196}, {
2197/* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw),
2198/* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNS("%ss:",OVERRIDE), TNSx("aaa",NORM),
2199/* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw),
2200/* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNS("%ds:",OVERRIDE), TNSx("aas",NORM),
2201}, {
2202/* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
2203/* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R),
2204/* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
2205/* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R),
2206}, {
2207/* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
2208/* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R),
2209/* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
2210/* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R),
2211}, {
2212/* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw),
2213/* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM),
2214/* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL),
2215/* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
2216}, {
2217/* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD),
2218/* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD),
2219/* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD),
2220/* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD),
2221}, {
2222/* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83),
2223/* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw),
2224/* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw),
2225/* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M),
2226}, {
2227/* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
2228/* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
2229/* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM),
2230/* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM),
2231}, {
2232/* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO),
2233/* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD),
2234/* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD),
2235/* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD),
2236}, {
2237/* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2238/* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR),
2239/* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
2240/* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR),
2241}, {
2242/* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM),
2243/* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw),
2244/* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM),
2245/* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM),
2246}, {
2247/* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3),
2248/* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1),
2249
2250/* 287 instructions. Note that although the indirect field */
2251/* indicates opFP1n2 for further decoding, this is not necessarily */
2252/* the case since the opFP arrays are not partitioned according to key1 */
2253/* and key2. opFP1n2 is given only to indicate that we haven't */
2254/* finished decoding the instruction. */
2255/* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
2256/* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2),
2257}, {
2258/* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD),
2259/* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P),
2260/* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD),
2261/* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V),
2262}, {
2263/* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX),
2264/* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7),
2265/* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM),
2266/* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF),
2267} };
2268
2269/* END CSTYLED */
2270
2271/*
2272 * common functions to decode and disassemble an x86 or amd64 instruction
2273 */
2274
2275/*
2276 * These are the individual fields of a REX prefix. Note that a REX
2277 * prefix with none of these set is still needed to:
2278 * - use the MOVSXD (sign extend 32 to 64 bits) instruction
2279 * - access the %sil, %dil, %bpl, %spl registers
2280 */
2281#define REX_W 0x08 /* 64 bit operand size when set */
2282#define REX_R 0x04 /* high order bit extension of ModRM reg field */
2283#define REX_X 0x02 /* high order bit extension of SIB index field */
2284#define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */
2285
2286/*
2287 * These are the individual fields of a VEX prefix.
2288 */
2289#define VEX_R 0x08 /* REX.R in 1's complement form */
2290#define VEX_X 0x04 /* REX.X in 1's complement form */
2291#define VEX_B 0x02 /* REX.B in 1's complement form */
2292/* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
2293#define VEX_L 0x04
2294#define VEX_W 0x08 /* opcode specific, use like REX.W */
2295#define VEX_m 0x1F /* VEX m-mmmm field */
2296#define VEX_v 0x78 /* VEX register specifier */
2297#define VEX_p 0x03 /* VEX pp field, opcode extension */
2298
2299/* VEX m-mmmm field, only used by three bytes prefix */
2300#define VEX_m_0F 0x01 /* implied 0F leading opcode byte */
2301#define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */
2302#define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */
2303
2304/* VEX pp field, providing equivalent functionality of a SIMD prefix */
2305#define VEX_p_66 0x01
2306#define VEX_p_F3 0x02
2307#define VEX_p_F2 0x03
2308
2309/*
2310 * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
2311 */
2312static int isize[] = {1, 2, 4, 4};
2313static int isize64[] = {1, 2, 4, 8};
2314
2315/*
2316 * Just a bunch of useful macros.
2317 */
2318#define WBIT(x) (x & 0x1) /* to get w bit */
2319#define REGNO(x) (x & 0x7) /* to get 3 bit register */
2320#define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */
2321#define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
2322#define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
2323
2324#define REG_ONLY 3 /* mode to indicate a register operand (not memory) */
2325
2326#define BYTE_OPND 0 /* w-bit value indicating byte register */
2327#define LONG_OPND 1 /* w-bit value indicating opnd_size register */
2328#define MM_OPND 2 /* "value" used to indicate a mmx reg */
2329#define XMM_OPND 3 /* "value" used to indicate a xmm reg */
2330#define SEG_OPND 4 /* "value" used to indicate a segment reg */
2331#define CONTROL_OPND 5 /* "value" used to indicate a control reg */
2332#define DEBUG_OPND 6 /* "value" used to indicate a debug reg */
2333#define TEST_OPND 7 /* "value" used to indicate a test reg */
2334#define WORD_OPND 8 /* w-bit value indicating word size reg */
2335#define YMM_OPND 9 /* "value" used to indicate a ymm reg */
2336
2337/*
2338 * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
2339 * there's not really a consistent scheme that we can use to know what the mode
2340 * is supposed to be for a given type. Various instructions, like VPGATHERDD,
2341 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
2342 * some registers match VEX_L, but the VSIB is always XMM.
2343 *
2344 * The simplest way to deal with this is to just define a table based on the
2345 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
2346 * them.
2347 *
2348 * We further have to subdivide this based on the value of VEX_W and the value
2349 * of VEX_L. The array is constructed to be indexed as:
2350 * [opcode - 0x90][VEX_W][VEX_L].
2351 */
2352/* w = 0, 0x90 */
2353typedef struct dis_gather_regs {
2354 uint_t dgr_arg0; /* src reg */
2355 uint_t dgr_arg1; /* vsib reg */
2356 uint_t dgr_arg2; /* dst reg */
2357 const char *dgr_suffix; /* suffix to append */
2358} dis_gather_regs_t;
2359
2360static dis_gather_regs_t dis_vgather[4][2][2] = {
2361 {
2362 /* op 0x90, W.0 */
2363 {
2364 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2365 { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2366 },
2367 /* op 0x90, W.1 */
2368 {
2369 { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2370 { YMM_OPND, XMM_OPND, YMM_OPND, "q" }
2371 }
2372 },
2373 {
2374 /* op 0x91, W.0 */
2375 {
2376 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2377 { XMM_OPND, YMM_OPND, XMM_OPND, "d" },
2378 },
2379 /* op 0x91, W.1 */
2380 {
2381 { XMM_OPND, XMM_OPND, XMM_OPND, "q" },
2382 { YMM_OPND, YMM_OPND, YMM_OPND, "q" },
2383 }
2384 },
2385 {
2386 /* op 0x92, W.0 */
2387 {
2388 { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2389 { YMM_OPND, YMM_OPND, YMM_OPND, "s" }
2390 },
2391 /* op 0x92, W.1 */
2392 {
2393 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2394 { YMM_OPND, XMM_OPND, YMM_OPND, "d" }
2395 }
2396 },
2397 {
2398 /* op 0x93, W.0 */
2399 {
2400 { XMM_OPND, XMM_OPND, XMM_OPND, "s" },
2401 { XMM_OPND, YMM_OPND, XMM_OPND, "s" }
2402 },
2403 /* op 0x93, W.1 */
2404 {
2405 { XMM_OPND, XMM_OPND, XMM_OPND, "d" },
2406 { YMM_OPND, YMM_OPND, YMM_OPND, "d" }
2407 }
2408 }
2409};
2410
2411/*
2412 * Get the next byte and separate the op code into the high and low nibbles.
2413 */
2414static int
2415dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low)
2416{
2417 int byte;
2418
2419 /*
2420 * x86 instructions have a maximum length of 15 bytes. Bail out if
2421 * we try to read more.
2422 */
2423 if (x->d86_len >= 15)
2424 return (x->d86_error = 1);
2425
2426 if (x->d86_error)
2427 return (1);
2428 byte = x->d86_get_byte(x->d86_data);
2429 if (byte < 0)
2430 return (x->d86_error = 1);
2431 x->d86_bytes[x->d86_len++] = byte;
2432 *low = byte & 0xf; /* ----xxxx low 4 bits */
2433 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */
2434 return (0);
2435}
2436
2437/*
2438 * Get and decode an SIB (scaled index base) byte
2439 */
2440static void
2441dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base)
2442{
2443 int byte;
2444
2445 if (x->d86_error)
2446 return;
2447
2448 byte = x->d86_get_byte(x->d86_data);
2449 if (byte < 0) {
2450 x->d86_error = 1;
2451 return;
2452 }
2453 x->d86_bytes[x->d86_len++] = byte;
2454
2455 *base = byte & 0x7;
2456 *index = (byte >> 3) & 0x7;
2457 *ss = (byte >> 6) & 0x3;
2458}
2459
2460/*
2461 * Get the byte following the op code and separate it into the
2462 * mode, register, and r/m fields.
2463 */
2464static void
2465dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m)
2466{
2467 if (x->d86_got_modrm == 0) {
2468 if (x->d86_rmindex == -1)
2469 x->d86_rmindex = x->d86_len;
2470 dtrace_get_SIB(x, mode, reg, r_m);
2471 x->d86_got_modrm = 1;
2472 }
2473}
2474
2475/*
2476 * Adjust register selection based on any REX prefix bits present.
2477 */
2478/*ARGSUSED*/
2479static void
2480dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m)
2481{
2482#pragma unused (mode)
2483 if (reg != NULL && r_m == NULL) {
2484 if (rex_prefix & REX_B)
2485 *reg += 8;
2486 } else {
2487 if (reg != NULL && (REX_R & rex_prefix) != 0)
2488 *reg += 8;
2489 if (r_m != NULL && (REX_B & rex_prefix) != 0)
2490 *r_m += 8;
2491 }
2492}
2493
2494/*
2495 * Adjust register selection based on any VEX prefix bits present.
2496 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
2497 */
2498/*ARGSUSED*/
2499static void
2500dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m)
2501{
2502#pragma unused (mode)
2503 if (reg != NULL && r_m == NULL) {
2504 if (!(vex_byte1 & VEX_B))
2505 *reg += 8;
2506 } else {
2507 if (reg != NULL && ((VEX_R & vex_byte1) == 0))
2508 *reg += 8;
2509 if (r_m != NULL && ((VEX_B & vex_byte1) == 0))
2510 *r_m += 8;
2511 }
2512}
2513
2514/*
2515 * Get an immediate operand of the given size, with sign extension.
2516 */
2517static void
2518dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex)
2519{
2520 int i;
2521 int byte;
2522 int valsize = 0;
2523
2524 if (x->d86_numopnds < (uint_t)opindex + 1)
2525 x->d86_numopnds = (uint_t)opindex + 1;
2526
2527 switch (wbit) {
2528 case BYTE_OPND:
2529 valsize = 1;
2530 break;
2531 case LONG_OPND:
2532 if (x->d86_opnd_size == SIZE16)
2533 valsize = 2;
2534 else if (x->d86_opnd_size == SIZE32)
2535 valsize = 4;
2536 else
2537 valsize = 8;
2538 break;
2539 case MM_OPND:
2540 case XMM_OPND:
2541 case YMM_OPND:
2542 case SEG_OPND:
2543 case CONTROL_OPND:
2544 case DEBUG_OPND:
2545 case TEST_OPND:
2546 valsize = size;
2547 break;
2548 case WORD_OPND:
2549 valsize = 2;
2550 break;
2551 }
2552 if (valsize < size)
2553 valsize = size;
2554
2555 if (x->d86_error)
2556 return;
2557 x->d86_opnd[opindex].d86_value = 0;
2558 for (i = 0; i < size; ++i) {
2559 byte = x->d86_get_byte(x->d86_data);
2560 if (byte < 0) {
2561 x->d86_error = 1;
2562 return;
2563 }
2564 x->d86_bytes[x->d86_len++] = byte;
2565 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8);
2566 }
2567 /* Do sign extension */
2568 if (x->d86_bytes[x->d86_len - 1] & 0x80) {
2569 for (; i < (int)sizeof (uint64_t); i++)
2570 x->d86_opnd[opindex].d86_value |=
2571 (uint64_t)0xff << (i * 8);
2572 }
2573#ifdef DIS_TEXT
2574 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2575 x->d86_opnd[opindex].d86_value_size = valsize;
2576 x->d86_imm_bytes += size;
2577#endif
2578}
2579
2580/*
2581 * Get an ip relative operand of the given size, with sign extension.
2582 */
2583static void
2584dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex)
2585{
2586 dtrace_imm_opnd(x, wbit, size, opindex);
2587#ifdef DIS_TEXT
2588 x->d86_opnd[opindex].d86_mode = MODE_IPREL;
2589#endif
2590}
2591
2592/*
2593 * Check to see if there is a segment override prefix pending.
2594 * If so, print it in the current 'operand' location and set
2595 * the override flag back to false.
2596 */
2597/*ARGSUSED*/
2598static void
2599dtrace_check_override(dis86_t *x, int opindex)
2600{
2601#ifdef DIS_TEXT
2602 if (x->d86_seg_prefix) {
2603 (void) strlcat(x->d86_opnd[opindex].d86_prefix,
2604 x->d86_seg_prefix, PFIXLEN);
2605 }
2606#else
2607 #pragma unused (opindex)
2608#endif
2609 x->d86_seg_prefix = NULL;
2610}
2611
2612
2613/*
2614 * Process a single instruction Register or Memory operand.
2615 *
2616 * mode = addressing mode from ModRM byte
2617 * r_m = r_m (or reg if mode == 3) field from ModRM byte
2618 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
2619 * o = index of operand that we are processing (0, 1 or 2)
2620 *
2621 * the value of reg or r_m must have already been adjusted for any REX prefix.
2622 */
2623/*ARGSUSED*/
2624static void
2625dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
2626{
2627 int have_SIB = 0; /* flag presence of scale-index-byte */
2628 uint_t ss; /* scale-factor from opcode */
2629 uint_t index; /* index register number */
2630 uint_t base; /* base register number */
2631 int dispsize; /* size of displacement in bytes */
2632#ifdef DIS_TEXT
2633 char *opnd = x->d86_opnd[opindex].d86_opnd;
2634#else
2635 #pragma unused (wbit)
2636#endif
2637
2638 if (x->d86_numopnds < (uint_t)opindex + 1)
2639 x->d86_numopnds = (uint_t)opindex + 1;
2640
2641 if (x->d86_error)
2642 return;
2643
2644 /*
2645 * first handle a simple register
2646 */
2647 if (mode == REG_ONLY) {
2648#ifdef DIS_TEXT
2649 switch (wbit) {
2650 case MM_OPND:
2651 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN);
2652 break;
2653 case XMM_OPND:
2654 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN);
2655 break;
2656 case YMM_OPND:
2657 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN);
2658 break;
2659 case SEG_OPND:
2660 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN);
2661 break;
2662 case CONTROL_OPND:
2663 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN);
2664 break;
2665 case DEBUG_OPND:
2666 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN);
2667 break;
2668 case TEST_OPND:
2669 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN);
2670 break;
2671 case BYTE_OPND:
2672 if (x->d86_rex_prefix == 0)
2673 (void) strlcat(opnd, dis_REG8[r_m], OPLEN);
2674 else
2675 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN);
2676 break;
2677 case WORD_OPND:
2678 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2679 break;
2680 case LONG_OPND:
2681 if (x->d86_opnd_size == SIZE16)
2682 (void) strlcat(opnd, dis_REG16[r_m], OPLEN);
2683 else if (x->d86_opnd_size == SIZE32)
2684 (void) strlcat(opnd, dis_REG32[r_m], OPLEN);
2685 else
2686 (void) strlcat(opnd, dis_REG64[r_m], OPLEN);
2687 break;
2688 }
2689#endif /* DIS_TEXT */
2690 return;
2691 }
2692
2693 /*
2694 * if symbolic representation, skip override prefix, if any
2695 */
2696 dtrace_check_override(x, opindex);
2697
2698 /*
2699 * Handle 16 bit memory references first, since they decode
2700 * the mode values more simply.
2701 * mode 1 is r_m + 8 bit displacement
2702 * mode 2 is r_m + 16 bit displacement
2703 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
2704 */
2705 if (x->d86_addr_size == SIZE16) {
2706 if ((mode == 0 && r_m == 6) || mode == 2)
2707 dtrace_imm_opnd(x, WORD_OPND, 2, opindex);
2708 else if (mode == 1)
2709 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex);
2710#ifdef DIS_TEXT
2711 if (mode == 0 && r_m == 6)
2712 x->d86_opnd[opindex].d86_mode = MODE_SIGNED;
2713 else if (mode == 0)
2714 x->d86_opnd[opindex].d86_mode = MODE_NONE;
2715 else
2716 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2717 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN);
2718#endif
2719 return;
2720 }
2721
2722 /*
2723 * 32 and 64 bit addressing modes are more complex since they
2724 * can involve an SIB (scaled index and base) byte to decode.
2725 */
2726 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) {
2727 have_SIB = 1;
2728 dtrace_get_SIB(x, &ss, &index, &base);
2729 if (x->d86_error)
2730 return;
2731 if (base != 5 || mode != 0)
2732 if (x->d86_rex_prefix & REX_B)
2733 base += 8;
2734 if (x->d86_rex_prefix & REX_X)
2735 index += 8;
2736 } else {
2737 base = r_m;
2738 }
2739
2740 /*
2741 * Compute the displacement size and get its bytes
2742 */
2743 dispsize = 0;
2744
2745 if (mode == 1)
2746 dispsize = 1;
2747 else if (mode == 2)
2748 dispsize = 4;
2749 else if ((r_m & 7) == EBP_REGNO ||
2750 (have_SIB && (base & 7) == EBP_REGNO))
2751 dispsize = 4;
2752
2753 if (dispsize > 0) {
2754 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND,
2755 dispsize, opindex);
2756 if (x->d86_error)
2757 return;
2758 }
2759
2760#ifdef DIS_TEXT
2761 if (dispsize > 0)
2762 x->d86_opnd[opindex].d86_mode = MODE_OFFSET;
2763
2764 if (have_SIB == 0) {
2765 if (x->d86_mode == SIZE32) {
2766 if (mode == 0)
2767 (void) strlcat(opnd, dis_addr32_mode0[r_m],
2768 OPLEN);
2769 else
2770 (void) strlcat(opnd, dis_addr32_mode12[r_m],
2771 OPLEN);
2772 } else {
2773 if (mode == 0) {
2774 (void) strlcat(opnd, dis_addr64_mode0[r_m],
2775 OPLEN);
2776 if (r_m == 5) {
2777 x->d86_opnd[opindex].d86_mode =
2778 MODE_RIPREL;
2779 }
2780 } else {
2781 (void) strlcat(opnd, dis_addr64_mode12[r_m],
2782 OPLEN);
2783 }
2784 }
2785 } else {
2786 uint_t need_paren = 0;
2787 char **regs;
2788 char **bregs;
2789 const char *const *sf;
2790 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */
2791 regs = (char **)dis_REG32;
2792 else
2793 regs = (char **)dis_REG64;
2794
2795 if (x->d86_vsib != 0) {
2796 if (wbit == YMM_OPND) /* NOTE this is not addr_size! */
2797 bregs = (char **)dis_YMMREG;
2798 else
2799 bregs = (char **)dis_XMMREG;
2800 sf = dis_vscale_factor;
2801 } else {
2802 bregs = regs;
2803 sf = dis_scale_factor;
2804 }
2805
2806 /*
2807 * print the base (if any)
2808 */
2809 if (base == EBP_REGNO && mode == 0) {
2810 if (index != ESP_REGNO || x->d86_vsib != 0) {
2811 (void) strlcat(opnd, "(", OPLEN);
2812 need_paren = 1;
2813 }
2814 } else {
2815 (void) strlcat(opnd, "(", OPLEN);
2816 (void) strlcat(opnd, regs[base], OPLEN);
2817 need_paren = 1;
2818 }
2819
2820 /*
2821 * print the index (if any)
2822 */
2823 if (index != ESP_REGNO || x->d86_vsib) {
2824 (void) strlcat(opnd, ",", OPLEN);
2825 (void) strlcat(opnd, bregs[index], OPLEN);
2826 (void) strlcat(opnd, sf[ss], OPLEN);
2827 } else
2828 if (need_paren)
2829 (void) strlcat(opnd, ")", OPLEN);
2830 }
2831#endif
2832}
2833
2834/*
2835 * Operand sequence for standard instruction involving one register
2836 * and one register/memory operand.
2837 * wbit indicates a byte(0) or opnd_size(1) operation
2838 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
2839 */
2840#define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \
2841 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2842 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2843 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2844 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \
2845}
2846
2847/*
2848 * Similar to above, but allows for the two operands to be of different
2849 * classes (ie. wbit).
2850 * wbit is for the r_m operand
2851 * w2 is for the reg operand
2852 */
2853#define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \
2854 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2855 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2856 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2857 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \
2858}
2859
2860/*
2861 * Similar, but for 2 operands plus an immediate.
2862 * vbit indicates direction
2863 * 0 for "opcode imm, r, r_m" or
2864 * 1 for "opcode imm, r_m, r"
2865 */
2866#define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
2867 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2868 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2869 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \
2870 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \
2871 dtrace_imm_opnd(x, wbit, immsize, 0); \
2872}
2873
2874/*
2875 * Similar, but for 2 operands plus two immediates.
2876 */
2877#define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
2878 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2879 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2880 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2881 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \
2882 dtrace_imm_opnd(x, wbit, immsize, 1); \
2883 dtrace_imm_opnd(x, wbit, immsize, 0); \
2884}
2885
2886/*
2887 * 1 operands plus two immediates.
2888 */
2889#define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
2890 dtrace_get_modrm(x, &mode, &reg, &r_m); \
2891 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m); \
2892 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2893 dtrace_imm_opnd(x, wbit, immsize, 1); \
2894 dtrace_imm_opnd(x, wbit, immsize, 0); \
2895}
2896
2897/*
2898 * Dissassemble a single x86 or amd64 instruction.
2899 *
2900 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
2901 * for interpreting instructions.
2902 *
2903 * returns non-zero for bad opcode
2904 */
2905int
2906dtrace_disx86(dis86_t *x, uint_t cpu_mode)
2907{
2908 instable_t *dp; /* decode table being used */
2909#ifdef DIS_TEXT
2910 uint_t i;
2911#endif
2912#ifdef DIS_MEM
2913 uint_t nomem = 0;
2914#define NOMEM (nomem = 1)
2915#else
2916#define NOMEM /* nothing */
2917#endif
2918 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */
2919 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */
2920 uint_t wbit = 0; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */
2921 uint_t w2; /* wbit value for second operand */
2922 uint_t vbit;
2923 uint_t mode = 0; /* mode value from ModRM byte */
2924 uint_t reg = 0; /* reg value from ModRM byte */
2925 uint_t r_m = 0; /* r_m value from ModRM byte */
2926
2927 uint_t opcode1 = 0; /* high nibble of 1st byte */
2928 uint_t opcode2 = 0; /* low nibble of 1st byte */
2929 uint_t opcode3 = 0; /* extra opcode bits usually from ModRM byte */
2930 uint_t opcode4 = 0; /* high nibble of 2nd byte */
2931 uint_t opcode5 = 0; /* low nibble of 2nd byte */
2932 uint_t opcode6 = 0; /* high nibble of 3rd byte */
2933 uint_t opcode7 = 0; /* low nibble of 3rd byte */
2934 uint_t opcode_bytes = 1;
2935
2936 /*
2937 * legacy prefixes come in 5 flavors, you should have only one of each
2938 */
2939 uint_t opnd_size_prefix = 0;
2940 uint_t addr_size_prefix = 0;
2941 uint_t segment_prefix = 0;
2942 uint_t lock_prefix = 0;
2943 uint_t rep_prefix = 0;
2944 uint_t rex_prefix = 0; /* amd64 register extension prefix */
2945
2946 /*
2947 * Intel VEX instruction encoding prefix and fields
2948 */
2949
2950 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
2951 uint_t vex_prefix = 0;
2952
2953 /*
2954 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
2955 * (for 3 bytes prefix)
2956 */
2957 uint_t vex_byte1 = 0;
2958
2959 /*
2960 * For 32-bit mode, it should prefetch the next byte to
2961 * distinguish between AVX and les/lds
2962 */
2963 uint_t vex_prefetch = 0;
2964
2965 uint_t vex_m = 0;
2966 uint_t vex_v = 0;
2967 uint_t vex_p = 0;
2968 uint_t vex_R = 1;
2969 uint_t vex_X = 1;
2970 uint_t vex_B = 1;
2971 uint_t vex_W = 0;
2972 uint_t vex_L = 0;
2973 dis_gather_regs_t *vreg;
2974
2975#ifdef DIS_TEXT
2976 /* Instruction name for BLS* family of instructions */
2977 char *blsinstr;
2978#endif
2979
2980 size_t off;
2981
2982 instable_t dp_mmx;
2983
2984 x->d86_len = 0;
2985 x->d86_rmindex = -1;
2986 x->d86_error = 0;
2987#ifdef DIS_TEXT
2988 x->d86_numopnds = 0;
2989 x->d86_seg_prefix = NULL;
2990 x->d86_mnem[0] = 0;
2991 for (i = 0; i < 4; ++i) {
2992 x->d86_opnd[i].d86_opnd[0] = 0;
2993 x->d86_opnd[i].d86_prefix[0] = 0;
2994 x->d86_opnd[i].d86_value_size = 0;
2995 x->d86_opnd[i].d86_value = 0;
2996 x->d86_opnd[i].d86_mode = MODE_NONE;
2997 }
2998#endif
2999 x->d86_rex_prefix = 0;
3000 x->d86_got_modrm = 0;
3001 x->d86_memsize = 0;
3002 x->d86_vsib = 0;
3003
3004 if (cpu_mode == SIZE16) {
3005 opnd_size = SIZE16;
3006 addr_size = SIZE16;
3007 } else if (cpu_mode == SIZE32) {
3008 opnd_size = SIZE32;
3009 addr_size = SIZE32;
3010 } else {
3011 opnd_size = SIZE32;
3012 addr_size = SIZE64;
3013 }
3014
3015 /*
3016 * Get one opcode byte and check for zero padding that follows
3017 * jump tables.
3018 */
3019 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3020 goto error;
3021
3022 if (opcode1 == 0 && opcode2 == 0 &&
3023 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) {
3024#ifdef DIS_TEXT
3025 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN);
3026#endif
3027 goto done;
3028 }
3029
3030 /*
3031 * Gather up legacy x86 prefix bytes.
3032 */
3033 for (;;) {
3034 uint_t *which_prefix = NULL;
3035
3036 dp = (instable_t *)&dis_distable[opcode1][opcode2];
3037
3038 switch (dp->it_adrmode) {
3039 case PREFIX:
3040 which_prefix = &rep_prefix;
3041 break;
3042 case LOCK:
3043 which_prefix = &lock_prefix;
3044 break;
3045 case OVERRIDE:
3046 which_prefix = &segment_prefix;
3047#ifdef DIS_TEXT
3048 x->d86_seg_prefix = (char *)dp->it_name;
3049#endif
3050 if (dp->it_invalid64 && cpu_mode == SIZE64)
3051 goto error;
3052 break;
3053 case AM:
3054 which_prefix = &addr_size_prefix;
3055 break;
3056 case DM:
3057 which_prefix = &opnd_size_prefix;
3058 break;
3059 }
3060 if (which_prefix == NULL)
3061 break;
3062 *which_prefix = (opcode1 << 4) | opcode2;
3063 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3064 goto error;
3065 }
3066
3067 /*
3068 * Handle amd64 mode PREFIX values.
3069 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
3070 * We might have a REX prefix (opcodes 0x40-0x4f)
3071 */
3072 if (cpu_mode == SIZE64) {
3073 if (segment_prefix != 0x64 && segment_prefix != 0x65)
3074 segment_prefix = 0;
3075
3076 if (opcode1 == 0x4) {
3077 rex_prefix = (opcode1 << 4) | opcode2;
3078 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3079 goto error;
3080 dp = (instable_t *)&dis_distable[opcode1][opcode2];
3081 } else if (opcode1 == 0xC &&
3082 (opcode2 == 0x4 || opcode2 == 0x5)) {
3083 /* AVX instructions */
3084 vex_prefix = (opcode1 << 4) | opcode2;
3085 x->d86_rex_prefix = 0x40;
3086 }
3087 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) {
3088 /* LDS, LES or AVX */
3089 dtrace_get_modrm(x, &mode, &reg, &r_m);
3090 vex_prefetch = 1;
3091
3092 if (mode == REG_ONLY) {
3093 /* AVX */
3094 vex_prefix = (opcode1 << 4) | opcode2;
3095 x->d86_rex_prefix = 0x40;
3096 opcode3 = (((mode << 3) | reg)>>1) & 0x0F;
3097 opcode4 = ((reg << 3) | r_m) & 0x0F;
3098 }
3099 }
3100
3101 if (vex_prefix == VEX_2bytes) {
3102 if (!vex_prefetch) {
3103 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3104 goto error;
3105 }
3106 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3;
3107 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2;
3108 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3;
3109 vex_p = opcode4 & VEX_p;
3110 /*
3111 * The vex.x and vex.b bits are not defined in two bytes
3112 * mode vex prefix, their default values are 1
3113 */
3114 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B;
3115
3116 if (vex_R == 0)
3117 x->d86_rex_prefix |= REX_R;
3118
3119 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3120 goto error;
3121
3122 switch (vex_p) {
3123 case VEX_p_66:
3124 dp = (instable_t *)
3125 &dis_opAVX660F[(opcode1 << 4) | opcode2];
3126 break;
3127 case VEX_p_F3:
3128 dp = (instable_t *)
3129 &dis_opAVXF30F[(opcode1 << 4) | opcode2];
3130 break;
3131 case VEX_p_F2:
3132 dp = (instable_t *)
3133 &dis_opAVXF20F [(opcode1 << 4) | opcode2];
3134 break;
3135 default:
3136 dp = (instable_t *)
3137 &dis_opAVX0F[opcode1][opcode2];
3138
3139 }
3140
3141 } else if (vex_prefix == VEX_3bytes) {
3142 if (!vex_prefetch) {
3143 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0)
3144 goto error;
3145 }
3146 vex_R = (opcode3 & VEX_R) >> 3;
3147 vex_X = (opcode3 & VEX_X) >> 2;
3148 vex_B = (opcode3 & VEX_B) >> 1;
3149 vex_m = (((opcode3 << 4) | opcode4) & VEX_m);
3150 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B);
3151
3152 if (vex_R == 0)
3153 x->d86_rex_prefix |= REX_R;
3154 if (vex_X == 0)
3155 x->d86_rex_prefix |= REX_X;
3156 if (vex_B == 0)
3157 x->d86_rex_prefix |= REX_B;
3158
3159 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0)
3160 goto error;
3161 vex_W = (opcode5 & VEX_W) >> 3;
3162 vex_L = (opcode6 & VEX_L) >> 2;
3163 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3;
3164 vex_p = opcode6 & VEX_p;
3165
3166 if (vex_W)
3167 x->d86_rex_prefix |= REX_W;
3168
3169 /* Only these three vex_m values valid; others are reserved */
3170 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) &&
3171 (vex_m != VEX_m_0F3A))
3172 goto error;
3173
3174 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0)
3175 goto error;
3176
3177 switch (vex_p) {
3178 case VEX_p_66:
3179 if (vex_m == VEX_m_0F) {
3180 dp = (instable_t *)
3181 &dis_opAVX660F
3182 [(opcode1 << 4) | opcode2];
3183 } else if (vex_m == VEX_m_0F38) {
3184 dp = (instable_t *)
3185 &dis_opAVX660F38
3186 [(opcode1 << 4) | opcode2];
3187 } else if (vex_m == VEX_m_0F3A) {
3188 dp = (instable_t *)
3189 &dis_opAVX660F3A
3190 [(opcode1 << 4) | opcode2];
3191 } else {
3192 goto error;
3193 }
3194 break;
3195 case VEX_p_F3:
3196 if (vex_m == VEX_m_0F) {
3197 dp = (instable_t *)
3198 &dis_opAVXF30F
3199 [(opcode1 << 4) | opcode2];
3200 } else if (vex_m == VEX_m_0F38) {
3201 dp = (instable_t *)
3202 &dis_opAVXF30F38
3203 [(opcode1 << 4) | opcode2];
3204 } else {
3205 goto error;
3206 }
3207 break;
3208 case VEX_p_F2:
3209 if (vex_m == VEX_m_0F) {
3210 dp = (instable_t *)
3211 &dis_opAVXF20F
3212 [(opcode1 << 4) | opcode2];
3213 } else if (vex_m == VEX_m_0F3A) {
3214 dp = (instable_t *)
3215 &dis_opAVXF20F3A
3216 [(opcode1 << 4) | opcode2];
3217 } else if (vex_m == VEX_m_0F38) {
3218 dp = (instable_t *)
3219 &dis_opAVXF20F38
3220 [(opcode1 << 4) | opcode2];
3221 } else {
3222 goto error;
3223 }
3224 break;
3225 default:
3226 dp = (instable_t *)
3227 &dis_opAVX0F[opcode1][opcode2];
3228
3229 }
3230 }
3231 if (vex_prefix) {
3232 if (dp->it_vexwoxmm) {
3233 wbit = LONG_OPND;
3234 } else {
3235 if (vex_L)
3236 wbit = YMM_OPND;
3237 else
3238 wbit = XMM_OPND;
3239 }
3240 }
3241
3242 /*
3243 * Deal with selection of operand and address size now.
3244 * Note that the REX.W bit being set causes opnd_size_prefix to be
3245 * ignored.
3246 */
3247 if (cpu_mode == SIZE64) {
3248 if ((rex_prefix & REX_W) || vex_W)
3249 opnd_size = SIZE64;
3250 else if (opnd_size_prefix)
3251 opnd_size = SIZE16;
3252
3253 if (addr_size_prefix)
3254 addr_size = SIZE32;
3255 } else if (cpu_mode == SIZE32) {
3256 if (opnd_size_prefix)
3257 opnd_size = SIZE16;
3258 if (addr_size_prefix)
3259 addr_size = SIZE16;
3260 } else {
3261 if (opnd_size_prefix)
3262 opnd_size = SIZE32;
3263 if (addr_size_prefix)
3264 addr_size = SIZE32;
3265 }
3266 /*
3267 * The pause instruction - a repz'd nop. This doesn't fit
3268 * with any of the other prefix goop added for SSE, so we'll
3269 * special-case it here.
3270 */
3271 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) {
3272 rep_prefix = 0;
3273 dp = (instable_t *)&dis_opPause;
3274 }
3275
3276 /*
3277 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
3278 * byte so we may need to perform a table indirection.
3279 */
3280 if (dp->it_indirect == (instable_t *)dis_op0F) {
3281 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0)
3282 goto error;
3283 opcode_bytes = 2;
3284 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) {
3285 uint_t subcode;
3286
3287 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3288 goto error;
3289 opcode_bytes = 3;
3290 subcode = ((opcode6 & 0x3) << 1) |
3291 ((opcode7 & 0x8) >> 3);
3292 dp = (instable_t *)&dis_op0F7123[opcode5][subcode];
3293 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) {
3294 dp = (instable_t *)&dis_op0FC8[0];
3295 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) {
3296 opcode_bytes = 3;
3297 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3298 goto error;
3299 if (opnd_size == SIZE16)
3300 opnd_size = SIZE32;
3301
3302 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7];
3303#ifdef DIS_TEXT
3304 if (LIT_STRNEQL(dp->it_name, "INVALID"))
3305 goto error;
3306#endif
3307 switch (dp->it_adrmode) {
3308 case XMMP:
3309 break;
3310 case XMMP_66r:
3311 case XMMPRM_66r:
3312 case XMM3PM_66r:
3313 if (opnd_size_prefix == 0) {
3314 goto error;
3315 }
3316 break;
3317 case XMMP_66o:
3318 if (opnd_size_prefix == 0) {
3319 /* SSSE3 MMX instructions */
3320 dp_mmx = *dp;
3321 dp = &dp_mmx;
3322 dp->it_adrmode = MMOPM_66o;
3323#ifdef DIS_MEM
3324 dp->it_size = 8;
3325#endif
3326 }
3327 break;
3328 default:
3329 goto error;
3330 }
3331 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) {
3332 opcode_bytes = 3;
3333 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0)
3334 goto error;
3335 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7];
3336
3337 /*
3338 * Both crc32 and movbe have the same 3rd opcode
3339 * byte of either 0xF0 or 0xF1, so we use another
3340 * indirection to distinguish between the two.
3341 */
3342 if (dp->it_indirect == (instable_t *)dis_op0F38F0 ||
3343 dp->it_indirect == (instable_t *)dis_op0F38F1) {
3344
3345 dp = dp->it_indirect;
3346 if (rep_prefix != 0xF2) {
3347 /* It is movbe */
3348 dp++;
3349 }
3350 }
3351
3352 /*
3353 * The adx family of instructions (adcx and adox)
3354 * continue the classic Intel tradition of abusing
3355 * arbitrary prefixes without actually meaning the
3356 * prefix bit. Therefore, if we find either the
3357 * opnd_size_prefix or rep_prefix we end up zeroing it
3358 * out after making our determination so as to ensure
3359 * that we don't get confused and accidentally print
3360 * repz prefixes and the like on these instructions.
3361 *
3362 * In addition, these instructions are actually much
3363 * closer to AVX instructions in semantics. Importantly,
3364 * they always default to having 32-bit operands.
3365 * However, if the CPU is in 64-bit mode, then and only
3366 * then, does it use REX.w promotes things to 64-bits
3367 * and REX.r allows 64-bit mode to use register r8-r15.
3368 */
3369 if (dp->it_indirect == (instable_t *)dis_op0F38F6) {
3370 dp = dp->it_indirect;
3371 if (opnd_size_prefix == 0 &&
3372 rep_prefix == 0xf3) {
3373 /* It is adox */
3374 dp++;
3375 } else if (opnd_size_prefix != 0x66 &&
3376 rep_prefix != 0) {
3377 /* It isn't adcx */
3378 goto error;
3379 }
3380 opnd_size_prefix = 0;
3381 rep_prefix = 0;
3382 opnd_size = SIZE32;
3383 if (rex_prefix & REX_W)
3384 opnd_size = SIZE64;
3385 }
3386
3387#ifdef DIS_TEXT
3388 if (LIT_STRNEQL(dp->it_name, "INVALID"))
3389 goto error;
3390#endif
3391 switch (dp->it_adrmode) {
3392 case ADX:
3393 case XMM:
3394 break;
3395 case RM_66r:
3396 case XMM_66r:
3397 case XMMM_66r:
3398 if (opnd_size_prefix == 0) {
3399 goto error;
3400 }
3401 break;
3402 case XMM_66o:
3403 if (opnd_size_prefix == 0) {
3404 /* SSSE3 MMX instructions */
3405 dp_mmx = *dp;
3406 dp = &dp_mmx;
3407 dp->it_adrmode = MM;
3408#ifdef DIS_MEM
3409 dp->it_size = 8;
3410#endif
3411 }
3412 break;
3413 case CRC32:
3414 if (rep_prefix != 0xF2) {
3415 goto error;
3416 }
3417 rep_prefix = 0;
3418 break;
3419 case MOVBE:
3420 if (rep_prefix != 0x0) {
3421 goto error;
3422 }
3423 break;
3424 default:
3425 goto error;
3426 }
3427 } else {
3428 dp = (instable_t *)&dis_op0F[opcode4][opcode5];
3429 }
3430 }
3431
3432 /*
3433 * If still not at a TERM decode entry, then a ModRM byte
3434 * exists and its fields further decode the instruction.
3435 */
3436 x->d86_got_modrm = 0;
3437 if (dp->it_indirect != TERM) {
3438 dtrace_get_modrm(x, &mode, &opcode3, &r_m);
3439 if (x->d86_error)
3440 goto error;
3441 reg = opcode3;
3442
3443 /*
3444 * decode 287 instructions (D8-DF) from opcodeN
3445 */
3446 if (opcode1 == 0xD && opcode2 >= 0x8) {
3447 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4)
3448 dp = (instable_t *)&dis_opFP5[r_m];
3449 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4)
3450 dp = (instable_t *)&dis_opFP7[opcode3];
3451 else if (opcode2 == 0xB && mode == 0x3)
3452 dp = (instable_t *)&dis_opFP6[opcode3];
3453 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4)
3454 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m];
3455 else if (mode == 0x3)
3456 dp = (instable_t *)
3457 &dis_opFP3[opcode2 - 8][opcode3];
3458 else
3459 dp = (instable_t *)
3460 &dis_opFP1n2[opcode2 - 8][opcode3];
3461 } else {
3462 dp = (instable_t *)dp->it_indirect + opcode3;
3463 }
3464 }
3465
3466 /*
3467 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
3468 * (sign extend 32bit to 64 bit)
3469 */
3470 if ((vex_prefix == 0) && cpu_mode == SIZE64 &&
3471 opcode1 == 0x6 && opcode2 == 0x3)
3472 {
3473 dp = (instable_t *)&dis_opMOVSLD;
3474 }
3475
3476 /*
3477 * at this point we should have a correct (or invalid) opcode
3478 */
3479 if ((cpu_mode == SIZE64 && dp->it_invalid64) ||
3480 (cpu_mode != SIZE64 && dp->it_invalid32))
3481 goto error;
3482 if (dp->it_indirect != TERM)
3483 goto error;
3484
3485 /*
3486 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do
3487 * need to include UNKNOWN below, as we may have instructions that
3488 * actually have a prefix, but don't exist in any other form.
3489 */
3490 switch (dp->it_adrmode) {
3491 case UNKNOWN:
3492 case MMO:
3493 case MMOIMPL:
3494 case MMO3P:
3495 case MMOM3:
3496 case MMOMS:
3497 case MMOPM:
3498 case MMOPRM:
3499 case MMOS:
3500 case XMMO:
3501 case XMMOM:
3502 case XMMOMS:
3503 case XMMOPM:
3504 case XMMOS:
3505 case XMMOMX:
3506 case XMMOX3:
3507 case XMMOXMM:
3508 /*
3509 * This is horrible. Some SIMD instructions take the
3510 * form 0x0F 0x?? ..., which is easily decoded using the
3511 * existing tables. Other SIMD instructions use various
3512 * prefix bytes to overload existing instructions. For
3513 * Example, addps is F0, 58, whereas addss is F3 (repz),
3514 * F0, 58. Presumably someone got a raise for this.
3515 *
3516 * If we see one of the instructions which can be
3517 * modified in this way (if we've got one of the SIMDO*
3518 * address modes), we'll check to see if the last prefix
3519 * was a repz. If it was, we strip the prefix from the
3520 * mnemonic, and we indirect using the dis_opSIMDrepz
3521 * table.
3522 */
3523
3524 /*
3525 * Calculate our offset in dis_op0F
3526 */
3527 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F))
3528 goto error;
3529
3530 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3531 sizeof (instable_t);
3532
3533 /*
3534 * Rewrite if this instruction used one of the magic prefixes.
3535 */
3536 if (rep_prefix) {
3537 if (rep_prefix == 0xf2)
3538 dp = (instable_t *)&dis_opSIMDrepnz[off];
3539 else
3540 dp = (instable_t *)&dis_opSIMDrepz[off];
3541 rep_prefix = 0;
3542 } else if (opnd_size_prefix) {
3543 dp = (instable_t *)&dis_opSIMDdata16[off];
3544 opnd_size_prefix = 0;
3545 if (opnd_size == SIZE16)
3546 opnd_size = SIZE32;
3547 }
3548 break;
3549
3550 case MG9:
3551 /*
3552 * More horribleness: the group 9 (0xF0 0xC7) instructions are
3553 * allowed an optional prefix of 0x66 or 0xF3. This is similar
3554 * to the SIMD business described above, but with a different
3555 * addressing mode (and an indirect table), so we deal with it
3556 * separately (if similarly).
3557 *
3558 * Intel further complicated this with the release of Ivy Bridge
3559 * where they overloaded these instructions based on the ModR/M
3560 * bytes. The VMX instructions have a mode of 0 since they are
3561 * memory instructions but rdrand instructions have a mode of
3562 * 0b11 (REG_ONLY) because they only operate on registers. While
3563 * there are different prefix formats, for now it is sufficient
3564 * to use a single different table.
3565 */
3566
3567 /*
3568 * Calculate our offset in dis_op0FC7 (the group 9 table)
3569 */
3570 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7))
3571 goto error;
3572
3573 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) /
3574 sizeof (instable_t);
3575
3576 /*
3577 * If we have a mode of 0b11 then we have to rewrite this.
3578 */
3579 dtrace_get_modrm(x, &mode, &reg, &r_m);
3580 if (mode == REG_ONLY) {
3581 dp = (instable_t *)&dis_op0FC7m3[off];
3582 break;
3583 }
3584
3585 /*
3586 * Rewrite if this instruction used one of the magic prefixes.
3587 */
3588 if (rep_prefix) {
3589 if (rep_prefix == 0xf3)
3590 dp = (instable_t *)&dis_opF30FC7[off];
3591 else
3592 goto error;
3593 rep_prefix = 0;
3594 } else if (opnd_size_prefix) {
3595 dp = (instable_t *)&dis_op660FC7[off];
3596 opnd_size_prefix = 0;
3597 if (opnd_size == SIZE16)
3598 opnd_size = SIZE32;
3599 }
3600 break;
3601
3602
3603 case MMOSH:
3604 /*
3605 * As with the "normal" SIMD instructions, the MMX
3606 * shuffle instructions are overloaded. These
3607 * instructions, however, are special in that they use
3608 * an extra byte, and thus an extra table. As of this
3609 * writing, they only use the opnd_size prefix.
3610 */
3611
3612 /*
3613 * Calculate our offset in dis_op0F7123
3614 */
3615 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 >
3616 sizeof (dis_op0F7123))
3617 goto error;
3618
3619 if (opnd_size_prefix) {
3620 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) /
3621 sizeof (instable_t);
3622 dp = (instable_t *)&dis_opSIMD7123[off];
3623 opnd_size_prefix = 0;
3624 if (opnd_size == SIZE16)
3625 opnd_size = SIZE32;
3626 }
3627 break;
3628 case MRw:
3629 if (rep_prefix) {
3630 if (rep_prefix == 0xf3) {
3631
3632 /*
3633 * Calculate our offset in dis_op0F
3634 */
3635 if ((uintptr_t)dp - (uintptr_t)dis_op0F
3636 > sizeof (dis_op0F))
3637 goto error;
3638
3639 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) /
3640 sizeof (instable_t);
3641
3642 dp = (instable_t *)&dis_opSIMDrepz[off];
3643 rep_prefix = 0;
3644 } else {
3645 goto error;
3646 }
3647 }
3648 break;
3649 }
3650
3651 /*
3652 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
3653 */
3654 if (cpu_mode == SIZE64)
3655 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop))
3656 opnd_size = SIZE64;
3657
3658#ifdef DIS_TEXT
3659 /*
3660 * At this point most instructions can format the opcode mnemonic
3661 * including the prefixes.
3662 */
3663 if (lock_prefix)
3664 (void) strlcat(x->d86_mnem, "lock ", OPLEN);
3665
3666 if (rep_prefix == 0xf2)
3667 (void) strlcat(x->d86_mnem, "repnz ", OPLEN);
3668 else if (rep_prefix == 0xf3)
3669 (void) strlcat(x->d86_mnem, "repz ", OPLEN);
3670
3671 if (cpu_mode == SIZE64 && addr_size_prefix)
3672 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN);
3673
3674 if (dp->it_adrmode != CBW &&
3675 dp->it_adrmode != CWD &&
3676 dp->it_adrmode != XMMSFNC) {
3677 if (LIT_STRNEQL(dp->it_name, "INVALID"))
3678 goto error;
3679 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN);
3680 if (dp->it_avxsuf && dp->it_suffix) {
3681 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d",
3682 OPLEN);
3683 } else if (dp->it_suffix) {
3684 char *types[] = {"", "w", "l", "q"};
3685 if (opcode_bytes == 2 && opcode4 == 4) {
3686 /* It's a cmovx.yy. Replace the suffix x */
3687 for (i = 5; i < OPLEN; i++) {
3688 if (x->d86_mnem[i] == '.')
3689 break;
3690 }
3691 x->d86_mnem[i - 1] = *types[opnd_size];
3692 } else if ((opnd_size == 2) && (opcode_bytes == 3) &&
3693 ((opcode6 == 1 && opcode7 == 6) ||
3694 (opcode6 == 2 && opcode7 == 2))) {
3695 /*
3696 * To handle PINSRD and PEXTRD
3697 */
3698 (void) strlcat(x->d86_mnem, "d", OPLEN);
3699 } else {
3700 (void) strlcat(x->d86_mnem, types[opnd_size],
3701 OPLEN);
3702 }
3703 }
3704 }
3705#endif
3706
3707 /*
3708 * Process operands based on the addressing modes.
3709 */
3710 x->d86_mode = cpu_mode;
3711 /*
3712 * In vex mode the rex_prefix has no meaning
3713 */
3714 if (!vex_prefix)
3715 x->d86_rex_prefix = rex_prefix;
3716 x->d86_opnd_size = opnd_size;
3717 x->d86_addr_size = addr_size;
3718 vbit = 0; /* initialize for mem/reg -> reg */
3719 switch (dp->it_adrmode) {
3720 /*
3721 * amd64 instruction to sign extend 32 bit reg/mem operands
3722 * into 64 bit register values
3723 */
3724 case MOVSXZ:
3725#ifdef DIS_TEXT
3726 if (rex_prefix == 0) {
3727 (void) strncpy(x->d86_mnem, "movzld", OPLEN);
3728 x->d86_mnem[OPLEN - 1] = '\0';
3729 }
3730#endif
3731 dtrace_get_modrm(x, &mode, &reg, &r_m);
3732 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3733 x->d86_opnd_size = SIZE64;
3734 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3735 x->d86_opnd_size = opnd_size = SIZE32;
3736 wbit = LONG_OPND;
3737 dtrace_get_operand(x, mode, r_m, wbit, 0);
3738 break;
3739
3740 /*
3741 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
3742 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
3743 * wbit lives in 2nd byte, note that operands
3744 * are different sized
3745 */
3746 case MOVZ:
3747 if (rex_prefix & REX_W) {
3748 /* target register size = 64 bit */
3749 x->d86_mnem[5] = 'q';
3750 }
3751 dtrace_get_modrm(x, &mode, &reg, &r_m);
3752 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3753 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3754 x->d86_opnd_size = opnd_size = SIZE16;
3755 wbit = WBIT(opcode5);
3756 dtrace_get_operand(x, mode, r_m, wbit, 0);
3757 break;
3758 case CRC32:
3759 opnd_size = SIZE32;
3760 if (rex_prefix & REX_W)
3761 opnd_size = SIZE64;
3762 x->d86_opnd_size = opnd_size;
3763
3764 dtrace_get_modrm(x, &mode, &reg, &r_m);
3765 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3766 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3767 wbit = WBIT(opcode7);
3768 if (opnd_size_prefix)
3769 x->d86_opnd_size = opnd_size = SIZE16;
3770 dtrace_get_operand(x, mode, r_m, wbit, 0);
3771 break;
3772 case MOVBE:
3773 opnd_size = SIZE32;
3774 if (rex_prefix & REX_W)
3775 opnd_size = SIZE64;
3776 x->d86_opnd_size = opnd_size;
3777
3778 dtrace_get_modrm(x, &mode, &reg, &r_m);
3779 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3780 wbit = WBIT(opcode7);
3781 if (opnd_size_prefix)
3782 x->d86_opnd_size = opnd_size = SIZE16;
3783 if (wbit) {
3784 /* reg -> mem */
3785 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
3786 dtrace_get_operand(x, mode, r_m, wbit, 1);
3787 } else {
3788 /* mem -> reg */
3789 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3790 dtrace_get_operand(x, mode, r_m, wbit, 0);
3791 }
3792 break;
3793
3794 /*
3795 * imul instruction, with either 8-bit or longer immediate
3796 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
3797 */
3798 case IMUL:
3799 wbit = LONG_OPND;
3800 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND,
3801 OPSIZE(opnd_size, opcode2 == 0x9), 1);
3802 break;
3803
3804 /* memory or register operand to register, with 'w' bit */
3805 case MRw:
3806 case ADX:
3807 wbit = WBIT(opcode2);
3808 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
3809 break;
3810
3811 /* register to memory or register operand, with 'w' bit */
3812 /* arpl happens to fit here also because it is odd */
3813 case RMw:
3814 if (opcode_bytes == 2)
3815 wbit = WBIT(opcode5);
3816 else
3817 wbit = WBIT(opcode2);
3818 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3819 break;
3820
3821 /* xaddb instruction */
3822 case XADDB:
3823 wbit = 0;
3824 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3825 break;
3826
3827 /* MMX register to memory or register operand */
3828 case MMS:
3829 case MMOS:
3830#ifdef DIS_TEXT
3831 wbit = !LIT_STRNEQL(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
3832#else
3833 wbit = LONG_OPND;
3834#endif
3835 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3836 break;
3837
3838 /* MMX register to memory */
3839 case MMOMS:
3840 dtrace_get_modrm(x, &mode, &reg, &r_m);
3841 if (mode == REG_ONLY)
3842 goto error;
3843 wbit = MM_OPND;
3844 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1);
3845 break;
3846
3847 /* Double shift. Has immediate operand specifying the shift. */
3848 case DSHIFT:
3849 wbit = LONG_OPND;
3850 dtrace_get_modrm(x, &mode, &reg, &r_m);
3851 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
3852 dtrace_get_operand(x, mode, r_m, wbit, 2);
3853 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
3854 dtrace_imm_opnd(x, wbit, 1, 0);
3855 break;
3856
3857 /*
3858 * Double shift. With no immediate operand, specifies using %cl.
3859 */
3860 case DSHIFTcl:
3861 wbit = LONG_OPND;
3862 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
3863 break;
3864
3865 /* immediate to memory or register operand */
3866 case IMlw:
3867 wbit = WBIT(opcode2);
3868 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3869 dtrace_get_operand(x, mode, r_m, wbit, 1);
3870 /*
3871 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
3872 */
3873 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0);
3874 break;
3875
3876 /* immediate to memory or register operand with the */
3877 /* 'w' bit present */
3878 case IMw:
3879 wbit = WBIT(opcode2);
3880 dtrace_get_modrm(x, &mode, &reg, &r_m);
3881 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3882 dtrace_get_operand(x, mode, r_m, wbit, 1);
3883 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
3884 break;
3885
3886 /* immediate to register with register in low 3 bits */
3887 /* of op code */
3888 case IR:
3889 /* w-bit here (with regs) is bit 3 */
3890 wbit = opcode2 >>3 & 0x1;
3891 reg = REGNO(opcode2);
3892 dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
3893 mode = REG_ONLY;
3894 r_m = reg;
3895 dtrace_get_operand(x, mode, r_m, wbit, 1);
3896 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0);
3897 break;
3898
3899 /* MMX immediate shift of register */
3900 case MMSH:
3901 case MMOSH:
3902 wbit = MM_OPND;
3903 goto mm_shift; /* in next case */
3904
3905 /* SIMD immediate shift of register */
3906 case XMMSH:
3907 wbit = XMM_OPND;
3908mm_shift:
3909 reg = REGNO(opcode7);
3910 dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
3911 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
3912 dtrace_imm_opnd(x, wbit, 1, 0);
3913 NOMEM;
3914 break;
3915
3916 /* accumulator to memory operand */
3917 case AO:
3918 vbit = 1;
3919 /*FALLTHROUGH*/
3920
3921 /* memory operand to accumulator */
3922 case OA:
3923 wbit = WBIT(opcode2);
3924 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit);
3925 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit);
3926#ifdef DIS_TEXT
3927 x->d86_opnd[vbit].d86_mode = MODE_OFFSET;
3928#endif
3929 break;
3930
3931
3932 /* segment register to memory or register operand */
3933 case SM:
3934 vbit = 1;
3935 /*FALLTHROUGH*/
3936
3937 /* memory or register operand to segment register */
3938 case MS:
3939 dtrace_get_modrm(x, &mode, &reg, &r_m);
3940 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3941 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit);
3942 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit);
3943 break;
3944
3945 /*
3946 * rotate or shift instructions, which may shift by 1 or
3947 * consult the cl register, depending on the 'v' bit
3948 */
3949 case Mv:
3950 vbit = VBIT(opcode2);
3951 wbit = WBIT(opcode2);
3952 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3953 dtrace_get_operand(x, mode, r_m, wbit, 1);
3954#ifdef DIS_TEXT
3955 if (vbit) {
3956 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN);
3957 } else {
3958 x->d86_opnd[0].d86_mode = MODE_SIGNED;
3959 x->d86_opnd[0].d86_value_size = 1;
3960 x->d86_opnd[0].d86_value = 1;
3961 }
3962#endif
3963 break;
3964 /*
3965 * immediate rotate or shift instructions
3966 */
3967 case MvI:
3968 wbit = WBIT(opcode2);
3969normal_imm_mem:
3970 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3971 dtrace_get_operand(x, mode, r_m, wbit, 1);
3972 dtrace_imm_opnd(x, wbit, 1, 0);
3973 break;
3974
3975 /* bit test instructions */
3976 case MIb:
3977 wbit = LONG_OPND;
3978 goto normal_imm_mem;
3979
3980 /* single memory or register operand with 'w' bit present */
3981 case Mw:
3982 wbit = WBIT(opcode2);
3983just_mem:
3984 dtrace_get_modrm(x, &mode, &reg, &r_m);
3985 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
3986 dtrace_get_operand(x, mode, r_m, wbit, 0);
3987 break;
3988
3989 case SWAPGS_RDTSCP:
3990 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) {
3991#ifdef DIS_TEXT
3992 (void) strncpy(x->d86_mnem, "swapgs", OPLEN);
3993 x->d86_mnem[OPLEN - 1] = '\0';
3994#endif
3995 NOMEM;
3996 break;
3997 } else if (mode == 3 && r_m == 1) {
3998#ifdef DIS_TEXT
3999 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN);
4000#endif
4001 NOMEM;
4002 break;
4003 }
4004
4005 /*FALLTHROUGH*/
4006
4007 /* prefetch instruction - memory operand, but no memory acess */
4008 case PREF:
4009 NOMEM;
4010 /*FALLTHROUGH*/
4011
4012 /* single memory or register operand */
4013 case M:
4014 case MG9:
4015 wbit = LONG_OPND;
4016 goto just_mem;
4017
4018 /* single memory or register byte operand */
4019 case Mb:
4020 wbit = BYTE_OPND;
4021 goto just_mem;
4022
4023 case VMx:
4024 if (mode == 3) {
4025#ifdef DIS_TEXT
4026 char *vminstr;
4027
4028 switch (r_m) {
4029 case 1:
4030 vminstr = "vmcall";
4031 break;
4032 case 2:
4033 vminstr = "vmlaunch";
4034 break;
4035 case 3:
4036 vminstr = "vmresume";
4037 break;
4038 case 4:
4039 vminstr = "vmxoff";
4040 break;
4041 default:
4042 goto error;
4043 }
4044
4045 (void) strncpy(x->d86_mnem, vminstr, OPLEN);
4046#else
4047 if (r_m < 1 || r_m > 4)
4048 goto error;
4049#endif
4050
4051 NOMEM;
4052 break;
4053 }
4054 /*FALLTHROUGH*/
4055 case SVM:
4056 if (mode == 3) {
4057#if DIS_TEXT
4058 char *vinstr;
4059
4060 switch (r_m) {
4061 case 0:
4062 vinstr = "vmrun";
4063 break;
4064 case 1:
4065 vinstr = "vmmcall";
4066 break;
4067 case 2:
4068 vinstr = "vmload";
4069 break;
4070 case 3:
4071 vinstr = "vmsave";
4072 break;
4073 case 4:
4074 vinstr = "stgi";
4075 break;
4076 case 5:
4077 vinstr = "clgi";
4078 break;
4079 case 6:
4080 vinstr = "skinit";
4081 break;
4082 case 7:
4083 vinstr = "invlpga";
4084 break;
4085 }
4086
4087 (void) strncpy(x->d86_mnem, vinstr, OPLEN);
4088#endif
4089 NOMEM;
4090 break;
4091 }
4092 /*FALLTHROUGH*/
4093 case MONITOR_MWAIT:
4094 if (mode == 3) {
4095 if (r_m == 0) {
4096#ifdef DIS_TEXT
4097 (void) strncpy(x->d86_mnem, "monitor", OPLEN);
4098 x->d86_mnem[OPLEN - 1] = '\0';
4099#endif
4100 NOMEM;
4101 break;
4102 } else if (r_m == 1) {
4103#ifdef DIS_TEXT
4104 (void) strncpy(x->d86_mnem, "mwait", OPLEN);
4105 x->d86_mnem[OPLEN - 1] = '\0';
4106#endif
4107 NOMEM;
4108 break;
4109 } else if (r_m == 2) {
4110#ifdef DIS_TEXT
4111 (void) strncpy(x->d86_mnem, "clac", OPLEN);
4112#endif
4113 NOMEM;
4114 break;
4115 } else if (r_m == 3) {
4116#ifdef DIS_TEXT
4117 (void) strncpy(x->d86_mnem, "stac", OPLEN);
4118#endif
4119 NOMEM;
4120 break;
4121 } else {
4122 goto error;
4123 }
4124 }
4125 /*FALLTHROUGH*/
4126 case XGETBV_XSETBV:
4127 if (mode == 3) {
4128 if (r_m == 0) {
4129#ifdef DIS_TEXT
4130 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN);
4131#endif
4132 NOMEM;
4133 break;
4134 } else if (r_m == 1) {
4135#ifdef DIS_TEXT
4136 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN);
4137#endif
4138 NOMEM;
4139 break;
4140 } else {
4141 goto error;
4142 }
4143
4144 }
4145 /*FALLTHROUGH*/
4146 case MO:
4147 /* Similar to M, but only memory (no direct registers) */
4148 wbit = LONG_OPND;
4149 dtrace_get_modrm(x, &mode, &reg, &r_m);
4150 if (mode == 3)
4151 goto error;
4152 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4153 dtrace_get_operand(x, mode, r_m, wbit, 0);
4154 break;
4155
4156 /* move special register to register or reverse if vbit */
4157 case SREG:
4158 switch (opcode5) {
4159
4160 case 2:
4161 vbit = 1;
4162 /*FALLTHROUGH*/
4163 case 0:
4164 wbit = CONTROL_OPND;
4165 break;
4166
4167 case 3:
4168 vbit = 1;
4169 /*FALLTHROUGH*/
4170 case 1:
4171 wbit = DEBUG_OPND;
4172 break;
4173
4174 case 6:
4175 vbit = 1;
4176 /*FALLTHROUGH*/
4177 case 4:
4178 wbit = TEST_OPND;
4179 break;
4180
4181 }
4182 dtrace_get_modrm(x, &mode, &reg, &r_m);
4183 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4184 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit);
4185 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit);
4186 NOMEM;
4187 break;
4188
4189 /*
4190 * single register operand with register in the low 3
4191 * bits of op code
4192 */
4193 case R:
4194 if (opcode_bytes == 2)
4195 reg = REGNO(opcode5);
4196 else
4197 reg = REGNO(opcode2);
4198 dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
4199 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
4200 NOMEM;
4201 break;
4202
4203 /*
4204 * register to accumulator with register in the low 3
4205 * bits of op code, xchg instructions
4206 */
4207 case RA:
4208 NOMEM;
4209 reg = REGNO(opcode2);
4210 dtrace_rex_adjust(rex_prefix, mode, &reg, NULL);
4211 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0);
4212 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1);
4213 break;
4214
4215 /*
4216 * single segment register operand, with register in
4217 * bits 3-4 of op code byte
4218 */
4219 case SEG:
4220 NOMEM;
4221 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3;
4222 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
4223 break;
4224
4225 /*
4226 * single segment register operand, with register in
4227 * bits 3-5 of op code
4228 */
4229 case LSEG:
4230 NOMEM;
4231 /* long seg reg from opcode */
4232 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7;
4233 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0);
4234 break;
4235
4236 /* memory or register operand to register */
4237 case MR:
4238 if (vex_prefetch)
4239 x->d86_got_modrm = 1;
4240 wbit = LONG_OPND;
4241 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
4242 break;
4243
4244 case RM:
4245 case RM_66r:
4246 wbit = LONG_OPND;
4247 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1);
4248 break;
4249
4250 /* MMX/SIMD-Int memory or mm reg to mm reg */
4251 case MM:
4252 case MMO:
4253#ifdef DIS_TEXT
4254 wbit = !LIT_STRNEQL(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
4255#else
4256 wbit = LONG_OPND;
4257#endif
4258 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
4259 break;
4260
4261 case MMOIMPL:
4262#ifdef DIS_TEXT
4263 wbit = !LIT_STRNEQL(dp->it_name, "movd") ? MM_OPND : LONG_OPND;
4264#else
4265 wbit = LONG_OPND;
4266#endif
4267 dtrace_get_modrm(x, &mode, &reg, &r_m);
4268 if (mode != REG_ONLY)
4269 goto error;
4270
4271 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4272 dtrace_get_operand(x, mode, r_m, wbit, 0);
4273 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1);
4274 mode = 0; /* change for memory access size... */
4275 break;
4276
4277 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */
4278 case MMO3P:
4279 wbit = MM_OPND;
4280 goto xmm3p;
4281 case XMM3P:
4282 wbit = XMM_OPND;
4283xmm3p:
4284 dtrace_get_modrm(x, &mode, &reg, &r_m);
4285 if (mode != REG_ONLY)
4286 goto error;
4287
4288 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1,
4289 1);
4290 NOMEM;
4291 break;
4292
4293 case XMM3PM_66r:
4294 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND,
4295 1, 0);
4296 break;
4297
4298 /* MMX/SIMD-Int predicated r32/mem to mm reg */
4299 case MMOPRM:
4300 wbit = LONG_OPND;
4301 w2 = MM_OPND;
4302 goto xmmprm;
4303 case XMMPRM:
4304 case XMMPRM_66r:
4305 wbit = LONG_OPND;
4306 w2 = XMM_OPND;
4307xmmprm:
4308 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1);
4309 break;
4310
4311 /* MMX/SIMD-Int predicated mm/mem to mm reg */
4312 case MMOPM:
4313 case MMOPM_66o:
4314 wbit = w2 = MM_OPND;
4315 goto xmmprm;
4316
4317 /* MMX/SIMD-Int mm reg to r32 */
4318 case MMOM3:
4319 NOMEM;
4320 dtrace_get_modrm(x, &mode, &reg, &r_m);
4321 if (mode != REG_ONLY)
4322 goto error;
4323 wbit = MM_OPND;
4324 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
4325 break;
4326
4327 /* SIMD memory or xmm reg operand to xmm reg */
4328 case XMM:
4329 case XMM_66o:
4330 case XMM_66r:
4331 case XMMO:
4332 case XMMXIMPL:
4333 wbit = XMM_OPND;
4334 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0);
4335
4336 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY)
4337 goto error;
4338
4339#ifdef DIS_TEXT
4340 /*
4341 * movlps and movhlps share opcodes. They differ in the
4342 * addressing modes allowed for their operands.
4343 * movhps and movlhps behave similarly.
4344 */
4345 if (mode == REG_ONLY) {
4346 if (LIT_STRNEQL(dp->it_name, "movlps")) {
4347 (void) strncpy(x->d86_mnem, "movhlps", OPLEN);
4348 x->d86_mnem[OPLEN - 1] = '\0';
4349 } else if (strcmp(dp->it_name, "movhps") == 0) {
4350 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
4351 x->d86_mnem[OPLEN - 1] = '\0';
4352 }
4353 }
4354#endif
4355 if (dp->it_adrmode == XMMXIMPL)
4356 mode = 0; /* change for memory access size... */
4357 break;
4358
4359 /* SIMD xmm reg to memory or xmm reg */
4360 case XMMS:
4361 case XMMOS:
4362 case XMMMS:
4363 case XMMOMS:
4364 dtrace_get_modrm(x, &mode, &reg, &r_m);
4365#ifdef DIS_TEXT
4366 if ((LIT_STRNEQL(dp->it_name, "movlps") ||
4367 LIT_STRNEQL(dp->it_name, "movhps") ||
4368 LIT_STRNEQL(dp->it_name, "movntps")) &&
4369 mode == REG_ONLY)
4370 goto error;
4371#endif
4372 wbit = XMM_OPND;
4373 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
4374 break;
4375
4376 /* SIMD memory to xmm reg */
4377 case XMMM:
4378 case XMMM_66r:
4379 case XMMOM:
4380 wbit = XMM_OPND;
4381 dtrace_get_modrm(x, &mode, &reg, &r_m);
4382#ifdef DIS_TEXT
4383 if (mode == REG_ONLY) {
4384 if (LIT_STRNEQL(dp->it_name, "movhps")) {
4385 (void) strncpy(x->d86_mnem, "movlhps", OPLEN);
4386 x->d86_mnem[OPLEN - 1] = '\0';
4387 } else
4388 goto error;
4389 }
4390#endif
4391 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4392 break;
4393
4394 /* SIMD memory or r32 to xmm reg */
4395 case XMM3MX:
4396 wbit = LONG_OPND;
4397 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4398 break;
4399
4400 case XMM3MXS:
4401 wbit = LONG_OPND;
4402 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1);
4403 break;
4404
4405 /* SIMD memory or mm reg to xmm reg */
4406 case XMMOMX:
4407 /* SIMD mm to xmm */
4408 case XMMMX:
4409 wbit = MM_OPND;
4410 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0);
4411 break;
4412
4413 /* SIMD memory or xmm reg to mm reg */
4414 case XMMXMM:
4415 case XMMOXMM:
4416 case XMMXM:
4417 wbit = XMM_OPND;
4418 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0);
4419 break;
4420
4421
4422 /* SIMD memory or xmm reg to r32 */
4423 case XMMXM3:
4424 wbit = XMM_OPND;
4425 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0);
4426 break;
4427
4428 /* SIMD xmm to r32 */
4429 case XMMX3:
4430 case XMMOX3:
4431 dtrace_get_modrm(x, &mode, &reg, &r_m);
4432 if (mode != REG_ONLY)
4433 goto error;
4434 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4435 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
4436 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1);
4437 NOMEM;
4438 break;
4439
4440 /* SIMD predicated memory or xmm reg with/to xmm reg */
4441 case XMMP:
4442 case XMMP_66r:
4443 case XMMP_66o:
4444 case XMMOPM:
4445 wbit = XMM_OPND;
4446 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1,
4447 1);
4448
4449#ifdef DIS_TEXT
4450 /*
4451 * cmpps and cmpss vary their instruction name based
4452 * on the value of imm8. Other XMMP instructions,
4453 * such as shufps, require explicit specification of
4454 * the predicate.
4455 */
4456 if (dp->it_name[0] == 'c' &&
4457 dp->it_name[1] == 'm' &&
4458 dp->it_name[2] == 'p' &&
4459 strlen(dp->it_name) == 5) {
4460 uchar_t pred = x->d86_opnd[0].d86_value & 0xff;
4461
4462 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *)))
4463 goto error;
4464
4465 (void) strncpy(x->d86_mnem, "cmp", OPLEN);
4466 x->d86_mnem[OPLEN - 1] = '\0';
4467 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred],
4468 OPLEN);
4469 (void) strlcat(x->d86_mnem,
4470 dp->it_name + strlen(dp->it_name) - 2,
4471 OPLEN);
4472 x->d86_opnd[0] = x->d86_opnd[1];
4473 x->d86_opnd[1] = x->d86_opnd[2];
4474 x->d86_numopnds = 2;
4475 }
4476#endif
4477 break;
4478
4479 case XMMX2I:
4480 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND,
4481 1);
4482 NOMEM;
4483 break;
4484
4485 case XMM2I:
4486 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1);
4487 NOMEM;
4488 break;
4489
4490 /* immediate operand to accumulator */
4491 case IA:
4492 wbit = WBIT(opcode2);
4493 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4494 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0);
4495 NOMEM;
4496 break;
4497
4498 /* memory or register operand to accumulator */
4499 case MA:
4500 wbit = WBIT(opcode2);
4501 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4502 dtrace_get_operand(x, mode, r_m, wbit, 0);
4503 break;
4504
4505 /* si register to di register used to reference memory */
4506 case SD:
4507#ifdef DIS_TEXT
4508 dtrace_check_override(x, 0);
4509 x->d86_numopnds = 2;
4510 if (addr_size == SIZE64) {
4511 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4512 OPLEN);
4513 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4514 OPLEN);
4515 } else if (addr_size == SIZE32) {
4516 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4517 OPLEN);
4518 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4519 OPLEN);
4520 } else {
4521 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4522 OPLEN);
4523 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4524 OPLEN);
4525 }
4526#endif
4527 wbit = LONG_OPND;
4528 break;
4529
4530 /* accumulator to di register */
4531 case AD:
4532 wbit = WBIT(opcode2);
4533#ifdef DIS_TEXT
4534 dtrace_check_override(x, 1);
4535 x->d86_numopnds = 2;
4536 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0);
4537 if (addr_size == SIZE64)
4538 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)",
4539 OPLEN);
4540 else if (addr_size == SIZE32)
4541 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)",
4542 OPLEN);
4543 else
4544 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)",
4545 OPLEN);
4546#endif
4547 break;
4548
4549 /* si register to accumulator */
4550 case SA:
4551 wbit = WBIT(opcode2);
4552#ifdef DIS_TEXT
4553 dtrace_check_override(x, 0);
4554 x->d86_numopnds = 2;
4555 if (addr_size == SIZE64)
4556 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)",
4557 OPLEN);
4558 else if (addr_size == SIZE32)
4559 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)",
4560 OPLEN);
4561 else
4562 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)",
4563 OPLEN);
4564 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1);
4565#endif
4566 break;
4567
4568 /*
4569 * single operand, a 16/32 bit displacement
4570 */
4571 case D:
4572 wbit = LONG_OPND;
4573 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4574 NOMEM;
4575 break;
4576
4577 /* jmp/call indirect to memory or register operand */
4578 case INM:
4579#ifdef DIS_TEXT
4580 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN);
4581#endif
4582 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m);
4583 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4584 wbit = LONG_OPND;
4585 break;
4586
4587 /*
4588 * for long jumps and long calls -- a new code segment
4589 * register and an offset in IP -- stored in object
4590 * code in reverse order. Note - not valid in amd64
4591 */
4592 case SO:
4593 dtrace_check_override(x, 1);
4594 wbit = LONG_OPND;
4595 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1);
4596#ifdef DIS_TEXT
4597 x->d86_opnd[1].d86_mode = MODE_SIGNED;
4598#endif
4599 /* will now get segment operand */
4600 dtrace_imm_opnd(x, wbit, 2, 0);
4601 break;
4602
4603 /*
4604 * jmp/call. single operand, 8 bit displacement.
4605 * added to current EIP in 'compofff'
4606 */
4607 case BD:
4608 dtrace_disp_opnd(x, BYTE_OPND, 1, 0);
4609 NOMEM;
4610 break;
4611
4612 /* single 32/16 bit immediate operand */
4613 case I:
4614 wbit = LONG_OPND;
4615 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0);
4616 break;
4617
4618 /* single 8 bit immediate operand */
4619 case Ib:
4620 wbit = LONG_OPND;
4621 dtrace_imm_opnd(x, wbit, 1, 0);
4622 break;
4623
4624 case ENTER:
4625 wbit = LONG_OPND;
4626 dtrace_imm_opnd(x, wbit, 2, 0);
4627 dtrace_imm_opnd(x, wbit, 1, 1);
4628 switch (opnd_size) {
4629 case SIZE64:
4630 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8;
4631 break;
4632 case SIZE32:
4633 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4;
4634 break;
4635 case SIZE16:
4636 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2;
4637 break;
4638 }
4639
4640 break;
4641
4642 /* 16-bit immediate operand */
4643 case RET:
4644 wbit = LONG_OPND;
4645 dtrace_imm_opnd(x, wbit, 2, 0);
4646 break;
4647
4648 /* single 8 bit port operand */
4649 case P:
4650 dtrace_check_override(x, 0);
4651 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4652 NOMEM;
4653 break;
4654
4655 /* single operand, dx register (variable port instruction) */
4656 case V:
4657 x->d86_numopnds = 1;
4658 dtrace_check_override(x, 0);
4659#ifdef DIS_TEXT
4660 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN);
4661#endif
4662 NOMEM;
4663 break;
4664
4665 /*
4666 * The int instruction, which has two forms:
4667 * int 3 (breakpoint) or
4668 * int n, where n is indicated in the subsequent
4669 * byte (format Ib). The int 3 instruction (opcode 0xCC),
4670 * where, although the 3 looks like an operand,
4671 * it is implied by the opcode. It must be converted
4672 * to the correct base and output.
4673 */
4674 case INT3:
4675#ifdef DIS_TEXT
4676 x->d86_numopnds = 1;
4677 x->d86_opnd[0].d86_mode = MODE_SIGNED;
4678 x->d86_opnd[0].d86_value_size = 1;
4679 x->d86_opnd[0].d86_value = 3;
4680#endif
4681 NOMEM;
4682 break;
4683
4684 /* single 8 bit immediate operand */
4685 case INTx:
4686 dtrace_imm_opnd(x, BYTE_OPND, 1, 0);
4687 NOMEM;
4688 break;
4689
4690 /* an unused byte must be discarded */
4691 case U:
4692 if (x->d86_get_byte(x->d86_data) < 0)
4693 goto error;
4694 x->d86_len++;
4695 NOMEM;
4696 break;
4697
4698 case CBW:
4699#ifdef DIS_TEXT
4700 if (opnd_size == SIZE16)
4701 (void) strlcat(x->d86_mnem, "cbtw", OPLEN);
4702 else if (opnd_size == SIZE32)
4703 (void) strlcat(x->d86_mnem, "cwtl", OPLEN);
4704 else
4705 (void) strlcat(x->d86_mnem, "cltq", OPLEN);
4706#endif
4707 wbit = LONG_OPND;
4708 NOMEM;
4709 break;
4710
4711 case CWD:
4712#ifdef DIS_TEXT
4713 if (opnd_size == SIZE16)
4714 (void) strlcat(x->d86_mnem, "cwtd", OPLEN);
4715 else if (opnd_size == SIZE32)
4716 (void) strlcat(x->d86_mnem, "cltd", OPLEN);
4717 else
4718 (void) strlcat(x->d86_mnem, "cqtd", OPLEN);
4719#endif
4720 wbit = LONG_OPND;
4721 NOMEM;
4722 break;
4723
4724 case XMMSFNC:
4725 /*
4726 * sfence is sfence if mode is REG_ONLY. If mode isn't
4727 * REG_ONLY, mnemonic should be 'clflush'.
4728 */
4729 dtrace_get_modrm(x, &mode, &reg, &r_m);
4730
4731 /* sfence doesn't take operands */
4732#ifdef DIS_TEXT
4733 if (mode == REG_ONLY) {
4734 (void) strlcat(x->d86_mnem, "sfence", OPLEN);
4735 } else {
4736 (void) strlcat(x->d86_mnem, "clflush", OPLEN);
4737 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4738 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4739 NOMEM;
4740 }
4741#else
4742 if (mode != REG_ONLY) {
4743 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4744 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
4745 NOMEM;
4746 }
4747#endif
4748 break;
4749
4750 /*
4751 * no disassembly, the mnemonic was all there was so go on
4752 */
4753 case NORM:
4754 if (dp->it_invalid32 && cpu_mode != SIZE64)
4755 goto error;
4756 NOMEM;
4757 /*FALLTHROUGH*/
4758 case IMPLMEM:
4759 break;
4760
4761 case XMMFENCE:
4762 /*
4763 * XRSTOR and LFENCE share the same opcode but differ in mode
4764 */
4765 dtrace_get_modrm(x, &mode, &reg, &r_m);
4766
4767 if (mode == REG_ONLY) {
4768 /*
4769 * Only the following exact byte sequences are allowed:
4770 *
4771 * 0f ae e8 lfence
4772 * 0f ae f0 mfence
4773 */
4774 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 &&
4775 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0)
4776 goto error;
4777 } else {
4778#ifdef DIS_TEXT
4779 (void) strncpy(x->d86_mnem, "xrstor", OPLEN);
4780#endif
4781 dtrace_rex_adjust(rex_prefix, mode, &reg, &r_m);
4782 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0);
4783 }
4784 break;
4785
4786 /* float reg */
4787 case F:
4788#ifdef DIS_TEXT
4789 x->d86_numopnds = 1;
4790 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN);
4791 x->d86_opnd[0].d86_opnd[4] = r_m + '0';
4792#endif
4793 NOMEM;
4794 break;
4795
4796 /* float reg to float reg, with ret bit present */
4797 case FF:
4798 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */
4799 /*FALLTHROUGH*/
4800 case FFC: /* case for vbit always = 0 */
4801#ifdef DIS_TEXT
4802 x->d86_numopnds = 2;
4803 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN);
4804 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN);
4805 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0';
4806#endif
4807 NOMEM;
4808 break;
4809
4810 /* AVX instructions */
4811 case VEX_MO:
4812 /* op(ModR/M.r/m) */
4813 x->d86_numopnds = 1;
4814 dtrace_get_modrm(x, &mode, &reg, &r_m);
4815#ifdef DIS_TEXT
4816 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3))
4817 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN);
4818#endif
4819 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4820 dtrace_get_operand(x, mode, r_m, wbit, 0);
4821 break;
4822 case VEX_RMrX:
4823 case FMA:
4824 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
4825 x->d86_numopnds = 3;
4826 dtrace_get_modrm(x, &mode, &reg, &r_m);
4827 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4828
4829 /*
4830 * In classic Intel fashion, the opcodes for all of the FMA
4831 * instructions all have two possible mnemonics which vary by
4832 * one letter, which is selected based on the value of the wbit.
4833 * When wbit is one, they have the 'd' suffix and when 'wbit' is
4834 * 0, they have the 's' suffix. Otherwise, the FMA instructions
4835 * are all a standard VEX_RMrX.
4836 */
4837#ifdef DIS_TEXT
4838 if (dp->it_adrmode == FMA) {
4839 size_t len = strlen(dp->it_name);
4840 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
4841 if (len + 1 < OPLEN) {
4842 (void) strncpy(x->d86_mnem + len,
4843 vex_W != 0 ? "d" : "s", OPLEN - len);
4844 }
4845 }
4846#endif
4847
4848 if (mode != REG_ONLY) {
4849 if ((dp == &dis_opAVXF20F[0x10]) ||
4850 (dp == &dis_opAVXF30F[0x10])) {
4851 /* vmovsd <m64>, <xmm> */
4852 /* or vmovss <m64>, <xmm> */
4853 x->d86_numopnds = 2;
4854 goto L_VEX_MX;
4855 }
4856 }
4857
4858 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4859 /*
4860 * VEX prefix uses the 1's complement form to encode the
4861 * XMM/YMM regs
4862 */
4863 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4864
4865 if ((dp == &dis_opAVXF20F[0x2A]) ||
4866 (dp == &dis_opAVXF30F[0x2A])) {
4867 /*
4868 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
4869 * <xmm>, <xmm>
4870 */
4871 wbit = LONG_OPND;
4872 }
4873#ifdef DIS_TEXT
4874 else if ((mode == REG_ONLY) &&
4875 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */
4876 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN);
4877 } else if ((mode == REG_ONLY) &&
4878 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */
4879 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN);
4880 }
4881#endif
4882 dtrace_get_operand(x, mode, r_m, wbit, 0);
4883
4884 break;
4885
4886 case VEX_VRMrX:
4887 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */
4888 x->d86_numopnds = 3;
4889 dtrace_get_modrm(x, &mode, &reg, &r_m);
4890 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4891
4892 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
4893 /*
4894 * VEX prefix uses the 1's complement form to encode the
4895 * XMM/YMM regs
4896 */
4897 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0);
4898
4899 dtrace_get_operand(x, mode, r_m, wbit, 1);
4900 break;
4901
4902 case VEX_SbVM:
4903 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */
4904 x->d86_numopnds = 3;
4905 x->d86_vsib = 1;
4906
4907 /*
4908 * All instructions that use VSIB are currently a mess. See the
4909 * comment around the dis_gather_regs_t structure definition.
4910 */
4911
4912 vreg = &dis_vgather[opcode2][vex_W][vex_L];
4913
4914#ifdef DIS_TEXT
4915 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN);
4916 (void) strlcat(x->d86_mnem + strlen(dp->it_name),
4917 vreg->dgr_suffix, OPLEN - strlen(dp->it_name));
4918#endif
4919
4920 dtrace_get_modrm(x, &mode, &reg, &r_m);
4921 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4922
4923 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2);
4924 /*
4925 * VEX prefix uses the 1's complement form to encode the
4926 * XMM/YMM regs
4927 */
4928 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0,
4929 0);
4930 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1);
4931 break;
4932
4933 case VEX_RRX:
4934 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
4935 x->d86_numopnds = 3;
4936
4937 dtrace_get_modrm(x, &mode, &reg, &r_m);
4938 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4939
4940 if (mode != REG_ONLY) {
4941 if ((dp == &dis_opAVXF20F[0x11]) ||
4942 (dp == &dis_opAVXF30F[0x11])) {
4943 /* vmovsd <xmm>, <m64> */
4944 /* or vmovss <xmm>, <m64> */
4945 x->d86_numopnds = 2;
4946 goto L_VEX_RM;
4947 }
4948 }
4949
4950 dtrace_get_operand(x, mode, r_m, wbit, 2);
4951 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
4952 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
4953 break;
4954
4955 case VEX_RMRX:
4956 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
4957 x->d86_numopnds = 4;
4958
4959 dtrace_get_modrm(x, &mode, &reg, &r_m);
4960 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
4961 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
4962 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
4963 if (dp == &dis_opAVX660F3A[0x18]) {
4964 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
4965 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1);
4966 } else if ((dp == &dis_opAVX660F3A[0x20]) ||
4967 (dp == & dis_opAVX660F[0xC4])) {
4968 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
4969 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
4970 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4971 } else if (dp == &dis_opAVX660F3A[0x22]) {
4972 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
4973#ifdef DIS_TEXT
4974 if (vex_W)
4975 x->d86_mnem[6] = 'q';
4976#endif
4977 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
4978 } else {
4979 dtrace_get_operand(x, mode, r_m, wbit, 1);
4980 }
4981
4982 /* one byte immediate number */
4983 dtrace_imm_opnd(x, wbit, 1, 0);
4984
4985 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
4986 if ((dp == &dis_opAVX660F3A[0x4A]) ||
4987 (dp == &dis_opAVX660F3A[0x4B]) ||
4988 (dp == &dis_opAVX660F3A[0x4C])) {
4989#ifdef DIS_TEXT
4990 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4;
4991#endif
4992 x->d86_opnd[0].d86_mode = MODE_NONE;
4993#ifdef DIS_TEXT
4994 if (vex_L)
4995 (void) strncpy(x->d86_opnd[0].d86_opnd,
4996 dis_YMMREG[regnum], OPLEN);
4997 else
4998 (void) strncpy(x->d86_opnd[0].d86_opnd,
4999 dis_XMMREG[regnum], OPLEN);
5000#endif
5001 }
5002 break;
5003
5004 case VEX_MX:
5005 /* ModR/M.reg := op(ModR/M.rm) */
5006 x->d86_numopnds = 2;
5007
5008 dtrace_get_modrm(x, &mode, &reg, &r_m);
5009 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5010L_VEX_MX:
5011
5012 if ((dp == &dis_opAVXF20F[0xE6]) ||
5013 (dp == &dis_opAVX660F[0x5A]) ||
5014 (dp == &dis_opAVX660F[0xE6])) {
5015 /* vcvtpd2dq <ymm>, <xmm> */
5016 /* or vcvtpd2ps <ymm>, <xmm> */
5017 /* or vcvttpd2dq <ymm>, <xmm> */
5018 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1);
5019 dtrace_get_operand(x, mode, r_m, wbit, 0);
5020 } else if ((dp == &dis_opAVXF30F[0xE6]) ||
5021 (dp == &dis_opAVX0F[0x5][0xA]) ||
5022 (dp == &dis_opAVX660F38[0x13]) ||
5023 (dp == &dis_opAVX660F38[0x18]) ||
5024 (dp == &dis_opAVX660F38[0x19]) ||
5025 (dp == &dis_opAVX660F38[0x58]) ||
5026 (dp == &dis_opAVX660F38[0x78]) ||
5027 (dp == &dis_opAVX660F38[0x79]) ||
5028 (dp == &dis_opAVX660F38[0x59])) {
5029 /* vcvtdq2pd <xmm>, <ymm> */
5030 /* or vcvtps2pd <xmm>, <ymm> */
5031 /* or vcvtph2ps <xmm>, <ymm> */
5032 /* or vbroadcasts* <xmm>, <ymm> */
5033 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5034 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0);
5035 } else if (dp == &dis_opAVX660F[0x6E]) {
5036 /* vmovd/q <reg/mem 32/64>, <xmm> */
5037#ifdef DIS_TEXT
5038 if (vex_W)
5039 x->d86_mnem[4] = 'q';
5040#endif
5041 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5042 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0);
5043 } else {
5044 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5045 dtrace_get_operand(x, mode, r_m, wbit, 0);
5046 }
5047
5048 break;
5049
5050 case VEX_MXI:
5051 /* ModR/M.reg := op(ModR/M.rm, imm8) */
5052 x->d86_numopnds = 3;
5053
5054 dtrace_get_modrm(x, &mode, &reg, &r_m);
5055 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5056
5057 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
5058 dtrace_get_operand(x, mode, r_m, wbit, 1);
5059
5060 /* one byte immediate number */
5061 dtrace_imm_opnd(x, wbit, 1, 0);
5062 break;
5063
5064 case VEX_XXI:
5065 /* VEX.vvvv := op(ModR/M.rm, imm8) */
5066 x->d86_numopnds = 3;
5067
5068 dtrace_get_modrm(x, &mode, &reg, &r_m);
5069#ifdef DIS_TEXT
5070 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg],
5071 OPLEN);
5072#endif
5073 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5074
5075 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
5076 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1);
5077
5078 /* one byte immediate number */
5079 dtrace_imm_opnd(x, wbit, 1, 0);
5080 break;
5081
5082 case VEX_MR:
5083 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
5084 if (dp == &dis_opAVX660F[0xC5]) {
5085 /* vpextrw <imm8>, <xmm>, <reg> */
5086 x->d86_numopnds = 2;
5087 vbit = 2;
5088 } else {
5089 x->d86_numopnds = 2;
5090 vbit = 1;
5091 }
5092
5093 dtrace_get_modrm(x, &mode, &reg, &r_m);
5094 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5095 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit);
5096 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1);
5097
5098 if (vbit == 2)
5099 dtrace_imm_opnd(x, wbit, 1, 0);
5100
5101 break;
5102
5103 case VEX_RRI:
5104 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
5105 x->d86_numopnds = 2;
5106
5107 dtrace_get_modrm(x, &mode, &reg, &r_m);
5108 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5109 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5110 dtrace_get_operand(x, mode, r_m, wbit, 0);
5111 break;
5112
5113 case VEX_RX:
5114 /* ModR/M.rm := op(ModR/M.reg) */
5115 /* vextractf128 || vcvtps2ph */
5116 if (dp == &dis_opAVX660F3A[0x19] ||
5117 dp == &dis_opAVX660F3A[0x1d]) {
5118 x->d86_numopnds = 3;
5119
5120 dtrace_get_modrm(x, &mode, &reg, &r_m);
5121 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5122
5123 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
5124 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5125
5126 /* one byte immediate number */
5127 dtrace_imm_opnd(x, wbit, 1, 0);
5128 break;
5129 }
5130
5131 x->d86_numopnds = 2;
5132
5133 dtrace_get_modrm(x, &mode, &reg, &r_m);
5134 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5135 dtrace_get_operand(x, mode, r_m, wbit, 1);
5136 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5137 break;
5138
5139 case VEX_RR:
5140 /* ModR/M.rm := op(ModR/M.reg) */
5141 x->d86_numopnds = 2;
5142
5143 dtrace_get_modrm(x, &mode, &reg, &r_m);
5144 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5145
5146 if (dp == &dis_opAVX660F[0x7E]) {
5147 /* vmovd/q <reg/mem 32/64>, <xmm> */
5148#ifdef DIS_TEXT
5149 if (vex_W)
5150 x->d86_mnem[4] = 'q';
5151#endif
5152 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1);
5153 } else
5154 dtrace_get_operand(x, mode, r_m, wbit, 1);
5155
5156 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5157 break;
5158
5159 case VEX_RRi:
5160 /* ModR/M.rm := op(ModR/M.reg, imm) */
5161 x->d86_numopnds = 3;
5162
5163 dtrace_get_modrm(x, &mode, &reg, &r_m);
5164 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5165
5166#ifdef DIS_TEXT
5167 if (dp == &dis_opAVX660F3A[0x16]) {
5168 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
5169 if (vex_W)
5170 x->d86_mnem[6] = 'q';
5171 }
5172#endif
5173 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
5174 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5175
5176 /* one byte immediate number */
5177 dtrace_imm_opnd(x, wbit, 1, 0);
5178 break;
5179 case VEX_RIM:
5180 /* ModR/M.rm := op(ModR/M.reg, imm) */
5181 x->d86_numopnds = 3;
5182
5183 dtrace_get_modrm(x, &mode, &reg, &r_m);
5184 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5185
5186 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2);
5187 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5188 /* one byte immediate number */
5189 dtrace_imm_opnd(x, wbit, 1, 0);
5190 break;
5191
5192 case VEX_RM:
5193 /* ModR/M.rm := op(ModR/M.reg) */
5194 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */
5195 x->d86_numopnds = 3;
5196
5197 dtrace_get_modrm(x, &mode, &reg, &r_m);
5198 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5199
5200 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2);
5201 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1);
5202 /* one byte immediate number */
5203 dtrace_imm_opnd(x, wbit, 1, 0);
5204 break;
5205 }
5206 x->d86_numopnds = 2;
5207
5208 dtrace_get_modrm(x, &mode, &reg, &r_m);
5209 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5210L_VEX_RM:
5211 vbit = 1;
5212 dtrace_get_operand(x, mode, r_m, wbit, vbit);
5213 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1);
5214
5215 break;
5216
5217 case VEX_RRM:
5218 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
5219 x->d86_numopnds = 3;
5220
5221 dtrace_get_modrm(x, &mode, &reg, &r_m);
5222 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5223 dtrace_get_operand(x, mode, r_m, wbit, 2);
5224 /* VEX use the 1's complement form encode the XMM/YMM regs */
5225 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5226 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0);
5227 break;
5228
5229 case VEX_RMX:
5230 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
5231 x->d86_numopnds = 3;
5232
5233 dtrace_get_modrm(x, &mode, &reg, &r_m);
5234 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5235 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2);
5236 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5237 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0);
5238 break;
5239
5240 case VEX_NONE:
5241#ifdef DIS_TEXT
5242 if (vex_L)
5243 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN);
5244#endif
5245 break;
5246 case BLS: {
5247
5248 /*
5249 * The BLS instructions are VEX instructions that are based on
5250 * VEX.0F38.F3; however, they are considered special group 17
5251 * and like everything else, they use the bits in 3-5 of the
5252 * MOD R/M to determine the sub instruction. Unlike many others
5253 * like the VMX instructions, these are valid both for memory
5254 * and register forms.
5255 */
5256
5257 dtrace_get_modrm(x, &mode, &reg, &r_m);
5258 dtrace_vex_adjust(vex_byte1, mode, &reg, &r_m);
5259
5260 switch (reg) {
5261 case 1:
5262#ifdef DIS_TEXT
5263 blsinstr = "blsr";
5264#endif
5265 break;
5266 case 2:
5267#ifdef DIS_TEXT
5268 blsinstr = "blsmsk";
5269#endif
5270 break;
5271 case 3:
5272#ifdef DIS_TEXT
5273 blsinstr = "blsi";
5274#endif
5275 break;
5276 default:
5277 goto error;
5278 }
5279
5280 x->d86_numopnds = 2;
5281#ifdef DIS_TEXT
5282 (void) strncpy(x->d86_mnem, blsinstr, OPLEN);
5283#endif
5284 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1);
5285 dtrace_get_operand(x, mode, r_m, wbit, 0);
5286 break;
5287 }
5288 /* an invalid op code */
5289 case AM:
5290 case DM:
5291 case OVERRIDE:
5292 case PREFIX:
5293 case UNKNOWN:
5294 NOMEM;
5295 default:
5296 goto error;
5297 } /* end switch */
5298 if (x->d86_error)
5299 goto error;
5300
5301done:
5302#ifdef DIS_MEM
5303 /*
5304 * compute the size of any memory accessed by the instruction
5305 */
5306 if (x->d86_memsize != 0) {
5307 return (0);
5308 } else if (dp->it_stackop) {
5309 switch (opnd_size) {
5310 case SIZE16:
5311 x->d86_memsize = 2;
5312 break;
5313 case SIZE32:
5314 x->d86_memsize = 4;
5315 break;
5316 case SIZE64:
5317 x->d86_memsize = 8;
5318 break;
5319 }
5320 } else if (nomem || mode == REG_ONLY) {
5321 x->d86_memsize = 0;
5322
5323 } else if (dp->it_size != 0) {
5324 /*
5325 * In 64 bit mode descriptor table entries
5326 * go up to 10 bytes and popf/pushf are always 8 bytes
5327 */
5328 if (x->d86_mode == SIZE64 && dp->it_size == 6)
5329 x->d86_memsize = 10;
5330 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 &&
5331 (opcode2 == 0xc || opcode2 == 0xd))
5332 x->d86_memsize = 8;
5333 else
5334 x->d86_memsize = dp->it_size;
5335
5336 } else if (wbit == 0) {
5337 x->d86_memsize = 1;
5338
5339 } else if (wbit == LONG_OPND) {
5340 if (opnd_size == SIZE64)
5341 x->d86_memsize = 8;
5342 else if (opnd_size == SIZE32)
5343 x->d86_memsize = 4;
5344 else
5345 x->d86_memsize = 2;
5346
5347 } else if (wbit == SEG_OPND) {
5348 x->d86_memsize = 4;
5349
5350 } else {
5351 x->d86_memsize = 8;
5352 }
5353#endif
5354 return (0);
5355
5356error:
5357#ifdef DIS_TEXT
5358 (void) strlcat(x->d86_mnem, "undef", OPLEN);
5359#endif
5360 return (1);
5361}
5362
5363#ifdef DIS_TEXT
5364
5365/*
5366 * Some instructions should have immediate operands printed
5367 * as unsigned integers. We compare against this table.
5368 */
5369static char *unsigned_ops[] = {
5370 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp",
5371 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl",
5372 0
5373};
5374
5375
5376static int
5377isunsigned_op(char *opcode)
5378{
5379 char *where;
5380 int i;
5381 int is_unsigned = 0;
5382
5383 /*
5384 * Work back to start of last mnemonic, since we may have
5385 * prefixes on some opcodes.
5386 */
5387 where = opcode + strlen(opcode) - 1;
5388 while (where > opcode && *where != ' ')
5389 --where;
5390 if (*where == ' ')
5391 ++where;
5392
5393 for (i = 0; unsigned_ops[i]; ++i) {
5394 if (strncmp(where, unsigned_ops[i],
5395 strlen(unsigned_ops[i])))
5396 continue;
5397 is_unsigned = 1;
5398 break;
5399 }
5400 return (is_unsigned);
5401}
5402
5403/*
5404 * Print a numeric immediate into end of buf, maximum length buflen.
5405 * The immediate may be an address or a displacement. Mask is set
5406 * for address size. If the immediate is a "small negative", or
5407 * if it's a negative displacement of any magnitude, print as -<absval>.
5408 * Respect the "octal" flag. "Small negative" is defined as "in the
5409 * interval [NEG_LIMIT, 0)".
5410 *
5411 * Also, "isunsigned_op()" instructions never print negatives.
5412 *
5413 * Return whether we decided to print a negative value or not.
5414 */
5415
5416#define NEG_LIMIT -255
5417enum {IMM, DISP};
5418enum {POS, TRY_NEG};
5419
5420static int
5421print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf,
5422 size_t buflen, int disp, int try_neg)
5423{
5424 int curlen;
5425 int64_t sv = (int64_t)usv;
5426 int octal = dis->d86_flags & DIS_F_OCTAL;
5427
5428 curlen = strlen(buf);
5429
5430 if (try_neg == TRY_NEG && sv < 0 &&
5431 (disp || sv >= NEG_LIMIT) &&
5432 !isunsigned_op(dis->d86_mnem)) {
5433 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5434 octal ? "-0%llo" : "-0x%llx", (-sv) & mask);
5435 return (1);
5436 } else {
5437 if (disp == DISP)
5438 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5439 octal ? "+0%llo" : "+0x%llx", usv & mask);
5440 else
5441 dis->d86_sprintf_func(buf + curlen, buflen - curlen,
5442 octal ? "0%llo" : "0x%llx", usv & mask);
5443 return (0);
5444
5445 }
5446}
5447
5448
5449static int
5450log2(int size)
5451{
5452 switch (size) {
5453 case 1: return (0);
5454 case 2: return (1);
5455 case 4: return (2);
5456 case 8: return (3);
5457 }
5458 return (0);
5459}
5460
5461/* ARGSUSED */
5462void
5463dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf,
5464 size_t buflen)
5465{
5466 uint64_t reltgt = 0;
5467 uint64_t tgt = 0;
5468 int curlen;
5469 int (*lookup)(void *, uint64_t, char *, size_t);
5470 int i;
5471 int64_t sv;
5472 uint64_t usv, mask, save_mask, save_usv;
5473 static uint64_t masks[] =
5474 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL};
5475 save_usv = 0;
5476
5477 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem);
5478
5479 /*
5480 * For PC-relative jumps, the pc is really the next pc after executing
5481 * this instruction, so increment it appropriately.
5482 */
5483 pc += dis->d86_len;
5484
5485 for (i = 0; i < dis->d86_numopnds; i++) {
5486 d86opnd_t *op = &dis->d86_opnd[i];
5487
5488 if (i != 0)
5489 (void) strlcat(buf, ",", buflen);
5490
5491 (void) strlcat(buf, op->d86_prefix, buflen);
5492
5493 /*
5494 * sv is for the signed, possibly-truncated immediate or
5495 * displacement; usv retains the original size and
5496 * unsignedness for symbol lookup.
5497 */
5498
5499 sv = usv = op->d86_value;
5500
5501 /*
5502 * About masks: for immediates that represent
5503 * addresses, the appropriate display size is
5504 * the effective address size of the instruction.
5505 * This includes MODE_OFFSET, MODE_IPREL, and
5506 * MODE_RIPREL. Immediates that are simply
5507 * immediate values should display in the operand's
5508 * size, however, since they don't represent addresses.
5509 */
5510
5511 /* d86_addr_size is SIZEnn, which is log2(real size) */
5512 mask = masks[dis->d86_addr_size];
5513
5514 /* d86_value_size and d86_imm_bytes are in bytes */
5515 if (op->d86_mode == MODE_SIGNED ||
5516 op->d86_mode == MODE_IMPLIED)
5517 mask = masks[log2(op->d86_value_size)];
5518
5519 switch (op->d86_mode) {
5520
5521 case MODE_NONE:
5522
5523 (void) strlcat(buf, op->d86_opnd, buflen);
5524 break;
5525
5526 case MODE_SIGNED:
5527 case MODE_IMPLIED:
5528 case MODE_OFFSET:
5529
5530 tgt = usv;
5531
5532 if (dis->d86_seg_prefix)
5533 (void) strlcat(buf, dis->d86_seg_prefix,
5534 buflen);
5535
5536 if (op->d86_mode == MODE_SIGNED ||
5537 op->d86_mode == MODE_IMPLIED) {
5538 (void) strlcat(buf, "$", buflen);
5539 }
5540
5541 if (print_imm(dis, usv, mask, buf, buflen,
5542 IMM, TRY_NEG) &&
5543 (op->d86_mode == MODE_SIGNED ||
5544 op->d86_mode == MODE_IMPLIED)) {
5545
5546 /*
5547 * We printed a negative value for an
5548 * immediate that wasn't a
5549 * displacement. Note that fact so we can
5550 * print the positive value as an
5551 * annotation.
5552 */
5553
5554 save_usv = usv;
5555 save_mask = mask;
5556 }
5557 (void) strlcat(buf, op->d86_opnd, buflen);
5558
5559 break;
5560
5561 case MODE_IPREL:
5562 case MODE_RIPREL:
5563
5564 reltgt = pc + sv;
5565
5566 switch (mode) {
5567 case SIZE16:
5568 reltgt = (uint16_t)reltgt;
5569 break;
5570 case SIZE32:
5571 reltgt = (uint32_t)reltgt;
5572 break;
5573 }
5574
5575 (void) print_imm(dis, usv, mask, buf, buflen,
5576 DISP, TRY_NEG);
5577
5578 if (op->d86_mode == MODE_RIPREL)
5579 (void) strlcat(buf, "(%rip)", buflen);
5580 break;
5581 }
5582 }
5583
5584 /*
5585 * The symbol lookups may result in false positives,
5586 * particularly on object files, where small numbers may match
5587 * the 0-relative non-relocated addresses of symbols.
5588 */
5589
5590 lookup = dis->d86_sym_lookup;
5591 if (tgt != 0) {
5592 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 &&
5593 lookup(dis->d86_data, tgt, NULL, 0) == 0) {
5594 (void) strlcat(buf, "\t<", buflen);
5595 curlen = strlen(buf);
5596 lookup(dis->d86_data, tgt, buf + curlen,
5597 buflen - curlen);
5598 (void) strlcat(buf, ">", buflen);
5599 }
5600
5601 /*
5602 * If we printed a negative immediate above, print the
5603 * positive in case our heuristic was unhelpful
5604 */
5605 if (save_usv) {
5606 (void) strlcat(buf, "\t<", buflen);
5607 (void) print_imm(dis, save_usv, save_mask, buf, buflen,
5608 IMM, POS);
5609 (void) strlcat(buf, ">", buflen);
5610 }
5611 }
5612
5613 if (reltgt != 0) {
5614 /* Print symbol or effective address for reltgt */
5615
5616 (void) strlcat(buf, "\t<", buflen);
5617 curlen = strlen(buf);
5618 lookup(dis->d86_data, reltgt, buf + curlen,
5619 buflen - curlen);
5620 (void) strlcat(buf, ">", buflen);
5621 }
5622}
5623
5624#endif /* DIS_TEXT */
5625