1/*
2 * Copyright (c) 2004-2006 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31
32#ifndef _MACH_I386__STRUCTS_H_
33#define _MACH_I386__STRUCTS_H_
34
35#include <sys/cdefs.h> /* __DARWIN_UNIX03 */
36#include <machine/types.h> /* __uint8_t */
37
38/*
39 * i386 is the structure that is exported to user threads for
40 * use in status/mutate calls. This structure should never change.
41 *
42 */
43
44#if __DARWIN_UNIX03
45#define _STRUCT_X86_THREAD_STATE32 struct __darwin_i386_thread_state
46_STRUCT_X86_THREAD_STATE32
47{
48 unsigned int __eax;
49 unsigned int __ebx;
50 unsigned int __ecx;
51 unsigned int __edx;
52 unsigned int __edi;
53 unsigned int __esi;
54 unsigned int __ebp;
55 unsigned int __esp;
56 unsigned int __ss;
57 unsigned int __eflags;
58 unsigned int __eip;
59 unsigned int __cs;
60 unsigned int __ds;
61 unsigned int __es;
62 unsigned int __fs;
63 unsigned int __gs;
64};
65#else /* !__DARWIN_UNIX03 */
66#define _STRUCT_X86_THREAD_STATE32 struct i386_thread_state
67_STRUCT_X86_THREAD_STATE32
68{
69 unsigned int eax;
70 unsigned int ebx;
71 unsigned int ecx;
72 unsigned int edx;
73 unsigned int edi;
74 unsigned int esi;
75 unsigned int ebp;
76 unsigned int esp;
77 unsigned int ss;
78 unsigned int eflags;
79 unsigned int eip;
80 unsigned int cs;
81 unsigned int ds;
82 unsigned int es;
83 unsigned int fs;
84 unsigned int gs;
85};
86#endif /* !__DARWIN_UNIX03 */
87
88/* This structure should be double-word aligned for performance */
89
90#if __DARWIN_UNIX03
91#define _STRUCT_FP_CONTROL struct __darwin_fp_control
92_STRUCT_FP_CONTROL
93{
94 unsigned short __invalid :1,
95 __denorm :1,
96 __zdiv :1,
97 __ovrfl :1,
98 __undfl :1,
99 __precis :1,
100 :2,
101 __pc :2,
102#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
103#define FP_PREC_24B 0
104#define FP_PREC_53B 2
105#define FP_PREC_64B 3
106#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
107 __rc :2,
108#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
109#define FP_RND_NEAR 0
110#define FP_RND_DOWN 1
111#define FP_RND_UP 2
112#define FP_CHOP 3
113#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
114 /*inf*/ :1,
115 :3;
116};
117typedef _STRUCT_FP_CONTROL __darwin_fp_control_t;
118#else /* !__DARWIN_UNIX03 */
119#define _STRUCT_FP_CONTROL struct fp_control
120_STRUCT_FP_CONTROL
121{
122 unsigned short invalid :1,
123 denorm :1,
124 zdiv :1,
125 ovrfl :1,
126 undfl :1,
127 precis :1,
128 :2,
129 pc :2,
130#define FP_PREC_24B 0
131#define FP_PREC_53B 2
132#define FP_PREC_64B 3
133 rc :2,
134#define FP_RND_NEAR 0
135#define FP_RND_DOWN 1
136#define FP_RND_UP 2
137#define FP_CHOP 3
138 /*inf*/ :1,
139 :3;
140};
141typedef _STRUCT_FP_CONTROL fp_control_t;
142#endif /* !__DARWIN_UNIX03 */
143
144/*
145 * Status word.
146 */
147
148#if __DARWIN_UNIX03
149#define _STRUCT_FP_STATUS struct __darwin_fp_status
150_STRUCT_FP_STATUS
151{
152 unsigned short __invalid :1,
153 __denorm :1,
154 __zdiv :1,
155 __ovrfl :1,
156 __undfl :1,
157 __precis :1,
158 __stkflt :1,
159 __errsumm :1,
160 __c0 :1,
161 __c1 :1,
162 __c2 :1,
163 __tos :3,
164 __c3 :1,
165 __busy :1;
166};
167typedef _STRUCT_FP_STATUS __darwin_fp_status_t;
168#else /* !__DARWIN_UNIX03 */
169#define _STRUCT_FP_STATUS struct fp_status
170_STRUCT_FP_STATUS
171{
172 unsigned short invalid :1,
173 denorm :1,
174 zdiv :1,
175 ovrfl :1,
176 undfl :1,
177 precis :1,
178 stkflt :1,
179 errsumm :1,
180 c0 :1,
181 c1 :1,
182 c2 :1,
183 tos :3,
184 c3 :1,
185 busy :1;
186};
187typedef _STRUCT_FP_STATUS fp_status_t;
188#endif /* !__DARWIN_UNIX03 */
189
190/* defn of 80bit x87 FPU or MMX register */
191
192#if __DARWIN_UNIX03
193#define _STRUCT_MMST_REG struct __darwin_mmst_reg
194_STRUCT_MMST_REG
195{
196 char __mmst_reg[10];
197 char __mmst_rsrv[6];
198};
199#else /* !__DARWIN_UNIX03 */
200#define _STRUCT_MMST_REG struct mmst_reg
201_STRUCT_MMST_REG
202{
203 char mmst_reg[10];
204 char mmst_rsrv[6];
205};
206#endif /* !__DARWIN_UNIX03 */
207
208
209/* defn of 128 bit XMM regs */
210
211#if __DARWIN_UNIX03
212#define _STRUCT_XMM_REG struct __darwin_xmm_reg
213_STRUCT_XMM_REG
214{
215 char __xmm_reg[16];
216};
217#else /* !__DARWIN_UNIX03 */
218#define _STRUCT_XMM_REG struct xmm_reg
219_STRUCT_XMM_REG
220{
221 char xmm_reg[16];
222};
223#endif /* !__DARWIN_UNIX03 */
224
225#if !defined(RC_HIDE_XNU_J137)
226/* defn of 256 bit YMM regs */
227
228#if __DARWIN_UNIX03
229#define _STRUCT_YMM_REG struct __darwin_ymm_reg
230_STRUCT_YMM_REG
231{
232 char __ymm_reg[32];
233};
234#else /* !__DARWIN_UNIX03 */
235#define _STRUCT_YMM_REG struct ymm_reg
236_STRUCT_YMM_REG
237{
238 char ymm_reg[32];
239};
240#endif /* !__DARWIN_UNIX03 */
241
242/* defn of 512 bit ZMM regs */
243
244#if __DARWIN_UNIX03
245#define _STRUCT_ZMM_REG struct __darwin_zmm_reg
246_STRUCT_ZMM_REG
247{
248 char __zmm_reg[64];
249};
250#else /* !__DARWIN_UNIX03 */
251#define _STRUCT_ZMM_REG struct zmm_reg
252_STRUCT_ZMM_REG
253{
254 char zmm_reg[64];
255};
256#endif /* !__DARWIN_UNIX03 */
257
258#if __DARWIN_UNIX03
259#define _STRUCT_OPMASK_REG struct __darwin_opmask_reg
260_STRUCT_OPMASK_REG
261{
262 char __opmask_reg[8];
263};
264#else /* !__DARWIN_UNIX03 */
265#define _STRUCT_OPMASK_REG struct opmask_reg
266_STRUCT_OPMASK_REG
267{
268 char opmask_reg[8];
269};
270#endif /* !__DARWIN_UNIX03 */
271#endif /* not RC_HIDE_XNU_J137 */
272
273/*
274 * Floating point state.
275 */
276
277#if !defined(_POSIX_C_SOURCE) || defined(_DARWIN_C_SOURCE)
278#define FP_STATE_BYTES 512 /* number of chars worth of data from fpu_fcw */
279#endif /* !_POSIX_C_SOURCE || _DARWIN_C_SOURCE */
280
281#if __DARWIN_UNIX03
282#define _STRUCT_X86_FLOAT_STATE32 struct __darwin_i386_float_state
283_STRUCT_X86_FLOAT_STATE32
284{
285 int __fpu_reserved[2];
286 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
287 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
288 __uint8_t __fpu_ftw; /* x87 FPU tag word */
289 __uint8_t __fpu_rsrv1; /* reserved */
290 __uint16_t __fpu_fop; /* x87 FPU Opcode */
291 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
292 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
293 __uint16_t __fpu_rsrv2; /* reserved */
294 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
295 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
296 __uint16_t __fpu_rsrv3; /* reserved */
297 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
298 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
299 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
300 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
301 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
302 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
303 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
304 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
305 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
306 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
307 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
308 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
309 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
310 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
311 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
312 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
313 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
314 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
315 char __fpu_rsrv4[14*16]; /* reserved */
316 int __fpu_reserved1;
317};
318
319#define _STRUCT_X86_AVX_STATE32 struct __darwin_i386_avx_state
320_STRUCT_X86_AVX_STATE32
321{
322 int __fpu_reserved[2];
323 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
324 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
325 __uint8_t __fpu_ftw; /* x87 FPU tag word */
326 __uint8_t __fpu_rsrv1; /* reserved */
327 __uint16_t __fpu_fop; /* x87 FPU Opcode */
328 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
329 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
330 __uint16_t __fpu_rsrv2; /* reserved */
331 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
332 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
333 __uint16_t __fpu_rsrv3; /* reserved */
334 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
335 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
336 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
337 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
338 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
339 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
340 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
341 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
342 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
343 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
344 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
345 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
346 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
347 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
348 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
349 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
350 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
351 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
352 char __fpu_rsrv4[14*16]; /* reserved */
353 int __fpu_reserved1;
354 char __avx_reserved1[64];
355 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
356 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
357 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
358 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
359 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
360 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
361 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
362 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
363};
364
365#if !defined(RC_HIDE_XNU_J137)
366#define _STRUCT_X86_AVX512_STATE32 struct __darwin_i386_avx512_state
367_STRUCT_X86_AVX512_STATE32
368{
369 int __fpu_reserved[2];
370 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
371 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
372 __uint8_t __fpu_ftw; /* x87 FPU tag word */
373 __uint8_t __fpu_rsrv1; /* reserved */
374 __uint16_t __fpu_fop; /* x87 FPU Opcode */
375 __uint32_t __fpu_ip; /* x87 FPU Instruction Pointer offset */
376 __uint16_t __fpu_cs; /* x87 FPU Instruction Pointer Selector */
377 __uint16_t __fpu_rsrv2; /* reserved */
378 __uint32_t __fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
379 __uint16_t __fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
380 __uint16_t __fpu_rsrv3; /* reserved */
381 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
382 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
383 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
384 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
385 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
386 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
387 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
388 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
389 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
390 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
391 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
392 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
393 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
394 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
395 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
396 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
397 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
398 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
399 char __fpu_rsrv4[14*16]; /* reserved */
400 int __fpu_reserved1;
401 char __avx_reserved1[64];
402 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
403 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
404 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
405 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
406 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
407 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
408 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
409 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
410 _STRUCT_OPMASK_REG __fpu_k0; /* K0 */
411 _STRUCT_OPMASK_REG __fpu_k1; /* K1 */
412 _STRUCT_OPMASK_REG __fpu_k2; /* K2 */
413 _STRUCT_OPMASK_REG __fpu_k3; /* K3 */
414 _STRUCT_OPMASK_REG __fpu_k4; /* K4 */
415 _STRUCT_OPMASK_REG __fpu_k5; /* K5 */
416 _STRUCT_OPMASK_REG __fpu_k6; /* K6 */
417 _STRUCT_OPMASK_REG __fpu_k7; /* K7 */
418 _STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
419 _STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
420 _STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
421 _STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
422 _STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
423 _STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
424 _STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
425 _STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
426};
427#endif /* not RC_HIDE_XNU_J137 */
428
429#else /* !__DARWIN_UNIX03 */
430#define _STRUCT_X86_FLOAT_STATE32 struct i386_float_state
431_STRUCT_X86_FLOAT_STATE32
432{
433 int fpu_reserved[2];
434 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
435 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
436 __uint8_t fpu_ftw; /* x87 FPU tag word */
437 __uint8_t fpu_rsrv1; /* reserved */
438 __uint16_t fpu_fop; /* x87 FPU Opcode */
439 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
440 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
441 __uint16_t fpu_rsrv2; /* reserved */
442 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
443 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
444 __uint16_t fpu_rsrv3; /* reserved */
445 __uint32_t fpu_mxcsr; /* MXCSR Register state */
446 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
447 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
448 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
449 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
450 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
451 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
452 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
453 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
454 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
455 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
456 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
457 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
458 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
459 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
460 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
461 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
462 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
463 char fpu_rsrv4[14*16]; /* reserved */
464 int fpu_reserved1;
465};
466
467#define _STRUCT_X86_AVX_STATE32 struct i386_avx_state
468_STRUCT_X86_AVX_STATE32
469{
470 int fpu_reserved[2];
471 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
472 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
473 __uint8_t fpu_ftw; /* x87 FPU tag word */
474 __uint8_t fpu_rsrv1; /* reserved */
475 __uint16_t fpu_fop; /* x87 FPU Opcode */
476 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
477 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
478 __uint16_t fpu_rsrv2; /* reserved */
479 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
480 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
481 __uint16_t fpu_rsrv3; /* reserved */
482 __uint32_t fpu_mxcsr; /* MXCSR Register state */
483 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
484 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
485 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
486 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
487 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
488 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
489 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
490 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
491 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
492 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
493 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
494 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
495 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
496 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
497 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
498 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
499 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
500 char fpu_rsrv4[14*16]; /* reserved */
501 int fpu_reserved1;
502 char avx_reserved1[64];
503 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
504 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
505 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
506 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
507 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
508 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
509 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
510 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
511};
512
513#if !defined(RC_HIDE_XNU_J137)
514#define _STRUCT_X86_AVX512_STATE32 struct i386_avx512_state
515_STRUCT_X86_AVX512_STATE32
516{
517 int fpu_reserved[2];
518 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
519 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
520 __uint8_t fpu_ftw; /* x87 FPU tag word */
521 __uint8_t fpu_rsrv1; /* reserved */
522 __uint16_t fpu_fop; /* x87 FPU Opcode */
523 __uint32_t fpu_ip; /* x87 FPU Instruction Pointer offset */
524 __uint16_t fpu_cs; /* x87 FPU Instruction Pointer Selector */
525 __uint16_t fpu_rsrv2; /* reserved */
526 __uint32_t fpu_dp; /* x87 FPU Instruction Operand(Data) Pointer offset */
527 __uint16_t fpu_ds; /* x87 FPU Instruction Operand(Data) Pointer Selector */
528 __uint16_t fpu_rsrv3; /* reserved */
529 __uint32_t fpu_mxcsr; /* MXCSR Register state */
530 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
531 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
532 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
533 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
534 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
535 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
536 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
537 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
538 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
539 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
540 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
541 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
542 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
543 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
544 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
545 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
546 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
547 char fpu_rsrv4[14*16]; /* reserved */
548 int fpu_reserved1;
549 char avx_reserved1[64];
550 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
551 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
552 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
553 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
554 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
555 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
556 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
557 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
558 _STRUCT_OPMASK_REG fpu_k0; /* K0 */
559 _STRUCT_OPMASK_REG fpu_k1; /* K1 */
560 _STRUCT_OPMASK_REG fpu_k2; /* K2 */
561 _STRUCT_OPMASK_REG fpu_k3; /* K3 */
562 _STRUCT_OPMASK_REG fpu_k4; /* K4 */
563 _STRUCT_OPMASK_REG fpu_k5; /* K5 */
564 _STRUCT_OPMASK_REG fpu_k6; /* K6 */
565 _STRUCT_OPMASK_REG fpu_k7; /* K7 */
566 _STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
567 _STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
568 _STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
569 _STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
570 _STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
571 _STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
572 _STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
573 _STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
574};
575#endif /* not RC_HIDE_XNU_J137 */
576
577#endif /* !__DARWIN_UNIX03 */
578
579#if __DARWIN_UNIX03
580#define _STRUCT_X86_EXCEPTION_STATE32 struct __darwin_i386_exception_state
581_STRUCT_X86_EXCEPTION_STATE32
582{
583 __uint16_t __trapno;
584 __uint16_t __cpu;
585 __uint32_t __err;
586 __uint32_t __faultvaddr;
587};
588#else /* !__DARWIN_UNIX03 */
589#define _STRUCT_X86_EXCEPTION_STATE32 struct i386_exception_state
590_STRUCT_X86_EXCEPTION_STATE32
591{
592 __uint16_t trapno;
593 __uint16_t cpu;
594 __uint32_t err;
595 __uint32_t faultvaddr;
596};
597#endif /* !__DARWIN_UNIX03 */
598
599#if __DARWIN_UNIX03
600#define _STRUCT_X86_DEBUG_STATE32 struct __darwin_x86_debug_state32
601_STRUCT_X86_DEBUG_STATE32
602{
603 unsigned int __dr0;
604 unsigned int __dr1;
605 unsigned int __dr2;
606 unsigned int __dr3;
607 unsigned int __dr4;
608 unsigned int __dr5;
609 unsigned int __dr6;
610 unsigned int __dr7;
611};
612#else /* !__DARWIN_UNIX03 */
613#define _STRUCT_X86_DEBUG_STATE32 struct x86_debug_state32
614_STRUCT_X86_DEBUG_STATE32
615{
616 unsigned int dr0;
617 unsigned int dr1;
618 unsigned int dr2;
619 unsigned int dr3;
620 unsigned int dr4;
621 unsigned int dr5;
622 unsigned int dr6;
623 unsigned int dr7;
624};
625#endif /* !__DARWIN_UNIX03 */
626
627/*
628 * 64 bit versions of the above
629 */
630
631#if __DARWIN_UNIX03
632#define _STRUCT_X86_THREAD_STATE64 struct __darwin_x86_thread_state64
633_STRUCT_X86_THREAD_STATE64
634{
635 __uint64_t __rax;
636 __uint64_t __rbx;
637 __uint64_t __rcx;
638 __uint64_t __rdx;
639 __uint64_t __rdi;
640 __uint64_t __rsi;
641 __uint64_t __rbp;
642 __uint64_t __rsp;
643 __uint64_t __r8;
644 __uint64_t __r9;
645 __uint64_t __r10;
646 __uint64_t __r11;
647 __uint64_t __r12;
648 __uint64_t __r13;
649 __uint64_t __r14;
650 __uint64_t __r15;
651 __uint64_t __rip;
652 __uint64_t __rflags;
653 __uint64_t __cs;
654 __uint64_t __fs;
655 __uint64_t __gs;
656};
657#else /* !__DARWIN_UNIX03 */
658#define _STRUCT_X86_THREAD_STATE64 struct x86_thread_state64
659_STRUCT_X86_THREAD_STATE64
660{
661 __uint64_t rax;
662 __uint64_t rbx;
663 __uint64_t rcx;
664 __uint64_t rdx;
665 __uint64_t rdi;
666 __uint64_t rsi;
667 __uint64_t rbp;
668 __uint64_t rsp;
669 __uint64_t r8;
670 __uint64_t r9;
671 __uint64_t r10;
672 __uint64_t r11;
673 __uint64_t r12;
674 __uint64_t r13;
675 __uint64_t r14;
676 __uint64_t r15;
677 __uint64_t rip;
678 __uint64_t rflags;
679 __uint64_t cs;
680 __uint64_t fs;
681 __uint64_t gs;
682};
683#endif /* !__DARWIN_UNIX03 */
684
685
686#if __DARWIN_UNIX03
687#define _STRUCT_X86_FLOAT_STATE64 struct __darwin_x86_float_state64
688_STRUCT_X86_FLOAT_STATE64
689{
690 int __fpu_reserved[2];
691 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
692 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
693 __uint8_t __fpu_ftw; /* x87 FPU tag word */
694 __uint8_t __fpu_rsrv1; /* reserved */
695 __uint16_t __fpu_fop; /* x87 FPU Opcode */
696
697 /* x87 FPU Instruction Pointer */
698 __uint32_t __fpu_ip; /* offset */
699 __uint16_t __fpu_cs; /* Selector */
700
701 __uint16_t __fpu_rsrv2; /* reserved */
702
703 /* x87 FPU Instruction Operand(Data) Pointer */
704 __uint32_t __fpu_dp; /* offset */
705 __uint16_t __fpu_ds; /* Selector */
706
707 __uint16_t __fpu_rsrv3; /* reserved */
708 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
709 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
710 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
711 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
712 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
713 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
714 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
715 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
716 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
717 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
718 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
719 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
720 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
721 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
722 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
723 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
724 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
725 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
726 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
727 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
728 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
729 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
730 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
731 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
732 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
733 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
734 char __fpu_rsrv4[6*16]; /* reserved */
735 int __fpu_reserved1;
736};
737
738#define _STRUCT_X86_AVX_STATE64 struct __darwin_x86_avx_state64
739_STRUCT_X86_AVX_STATE64
740{
741 int __fpu_reserved[2];
742 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
743 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
744 __uint8_t __fpu_ftw; /* x87 FPU tag word */
745 __uint8_t __fpu_rsrv1; /* reserved */
746 __uint16_t __fpu_fop; /* x87 FPU Opcode */
747
748 /* x87 FPU Instruction Pointer */
749 __uint32_t __fpu_ip; /* offset */
750 __uint16_t __fpu_cs; /* Selector */
751
752 __uint16_t __fpu_rsrv2; /* reserved */
753
754 /* x87 FPU Instruction Operand(Data) Pointer */
755 __uint32_t __fpu_dp; /* offset */
756 __uint16_t __fpu_ds; /* Selector */
757
758 __uint16_t __fpu_rsrv3; /* reserved */
759 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
760 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
761 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
762 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
763 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
764 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
765 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
766 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
767 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
768 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
769 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
770 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
771 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
772 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
773 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
774 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
775 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
776 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
777 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
778 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
779 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
780 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
781 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
782 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
783 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
784 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
785 char __fpu_rsrv4[6*16]; /* reserved */
786 int __fpu_reserved1;
787 char __avx_reserved1[64];
788 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
789 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
790 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
791 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
792 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
793 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
794 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
795 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
796 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
797 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
798 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
799 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
800 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
801 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
802 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
803 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
804};
805
806#if !defined(RC_HIDE_XNU_J137)
807#define _STRUCT_X86_AVX512_STATE64 struct __darwin_x86_avx512_state64
808_STRUCT_X86_AVX512_STATE64
809{
810 int __fpu_reserved[2];
811 _STRUCT_FP_CONTROL __fpu_fcw; /* x87 FPU control word */
812 _STRUCT_FP_STATUS __fpu_fsw; /* x87 FPU status word */
813 __uint8_t __fpu_ftw; /* x87 FPU tag word */
814 __uint8_t __fpu_rsrv1; /* reserved */
815 __uint16_t __fpu_fop; /* x87 FPU Opcode */
816
817 /* x87 FPU Instruction Pointer */
818 __uint32_t __fpu_ip; /* offset */
819 __uint16_t __fpu_cs; /* Selector */
820
821 __uint16_t __fpu_rsrv2; /* reserved */
822
823 /* x87 FPU Instruction Operand(Data) Pointer */
824 __uint32_t __fpu_dp; /* offset */
825 __uint16_t __fpu_ds; /* Selector */
826
827 __uint16_t __fpu_rsrv3; /* reserved */
828 __uint32_t __fpu_mxcsr; /* MXCSR Register state */
829 __uint32_t __fpu_mxcsrmask; /* MXCSR mask */
830 _STRUCT_MMST_REG __fpu_stmm0; /* ST0/MM0 */
831 _STRUCT_MMST_REG __fpu_stmm1; /* ST1/MM1 */
832 _STRUCT_MMST_REG __fpu_stmm2; /* ST2/MM2 */
833 _STRUCT_MMST_REG __fpu_stmm3; /* ST3/MM3 */
834 _STRUCT_MMST_REG __fpu_stmm4; /* ST4/MM4 */
835 _STRUCT_MMST_REG __fpu_stmm5; /* ST5/MM5 */
836 _STRUCT_MMST_REG __fpu_stmm6; /* ST6/MM6 */
837 _STRUCT_MMST_REG __fpu_stmm7; /* ST7/MM7 */
838 _STRUCT_XMM_REG __fpu_xmm0; /* XMM 0 */
839 _STRUCT_XMM_REG __fpu_xmm1; /* XMM 1 */
840 _STRUCT_XMM_REG __fpu_xmm2; /* XMM 2 */
841 _STRUCT_XMM_REG __fpu_xmm3; /* XMM 3 */
842 _STRUCT_XMM_REG __fpu_xmm4; /* XMM 4 */
843 _STRUCT_XMM_REG __fpu_xmm5; /* XMM 5 */
844 _STRUCT_XMM_REG __fpu_xmm6; /* XMM 6 */
845 _STRUCT_XMM_REG __fpu_xmm7; /* XMM 7 */
846 _STRUCT_XMM_REG __fpu_xmm8; /* XMM 8 */
847 _STRUCT_XMM_REG __fpu_xmm9; /* XMM 9 */
848 _STRUCT_XMM_REG __fpu_xmm10; /* XMM 10 */
849 _STRUCT_XMM_REG __fpu_xmm11; /* XMM 11 */
850 _STRUCT_XMM_REG __fpu_xmm12; /* XMM 12 */
851 _STRUCT_XMM_REG __fpu_xmm13; /* XMM 13 */
852 _STRUCT_XMM_REG __fpu_xmm14; /* XMM 14 */
853 _STRUCT_XMM_REG __fpu_xmm15; /* XMM 15 */
854 char __fpu_rsrv4[6*16]; /* reserved */
855 int __fpu_reserved1;
856 char __avx_reserved1[64];
857 _STRUCT_XMM_REG __fpu_ymmh0; /* YMMH 0 */
858 _STRUCT_XMM_REG __fpu_ymmh1; /* YMMH 1 */
859 _STRUCT_XMM_REG __fpu_ymmh2; /* YMMH 2 */
860 _STRUCT_XMM_REG __fpu_ymmh3; /* YMMH 3 */
861 _STRUCT_XMM_REG __fpu_ymmh4; /* YMMH 4 */
862 _STRUCT_XMM_REG __fpu_ymmh5; /* YMMH 5 */
863 _STRUCT_XMM_REG __fpu_ymmh6; /* YMMH 6 */
864 _STRUCT_XMM_REG __fpu_ymmh7; /* YMMH 7 */
865 _STRUCT_XMM_REG __fpu_ymmh8; /* YMMH 8 */
866 _STRUCT_XMM_REG __fpu_ymmh9; /* YMMH 9 */
867 _STRUCT_XMM_REG __fpu_ymmh10; /* YMMH 10 */
868 _STRUCT_XMM_REG __fpu_ymmh11; /* YMMH 11 */
869 _STRUCT_XMM_REG __fpu_ymmh12; /* YMMH 12 */
870 _STRUCT_XMM_REG __fpu_ymmh13; /* YMMH 13 */
871 _STRUCT_XMM_REG __fpu_ymmh14; /* YMMH 14 */
872 _STRUCT_XMM_REG __fpu_ymmh15; /* YMMH 15 */
873 _STRUCT_OPMASK_REG __fpu_k0; /* K0 */
874 _STRUCT_OPMASK_REG __fpu_k1; /* K1 */
875 _STRUCT_OPMASK_REG __fpu_k2; /* K2 */
876 _STRUCT_OPMASK_REG __fpu_k3; /* K3 */
877 _STRUCT_OPMASK_REG __fpu_k4; /* K4 */
878 _STRUCT_OPMASK_REG __fpu_k5; /* K5 */
879 _STRUCT_OPMASK_REG __fpu_k6; /* K6 */
880 _STRUCT_OPMASK_REG __fpu_k7; /* K7 */
881 _STRUCT_YMM_REG __fpu_zmmh0; /* ZMMH 0 */
882 _STRUCT_YMM_REG __fpu_zmmh1; /* ZMMH 1 */
883 _STRUCT_YMM_REG __fpu_zmmh2; /* ZMMH 2 */
884 _STRUCT_YMM_REG __fpu_zmmh3; /* ZMMH 3 */
885 _STRUCT_YMM_REG __fpu_zmmh4; /* ZMMH 4 */
886 _STRUCT_YMM_REG __fpu_zmmh5; /* ZMMH 5 */
887 _STRUCT_YMM_REG __fpu_zmmh6; /* ZMMH 6 */
888 _STRUCT_YMM_REG __fpu_zmmh7; /* ZMMH 7 */
889 _STRUCT_YMM_REG __fpu_zmmh8; /* ZMMH 8 */
890 _STRUCT_YMM_REG __fpu_zmmh9; /* ZMMH 9 */
891 _STRUCT_YMM_REG __fpu_zmmh10; /* ZMMH 10 */
892 _STRUCT_YMM_REG __fpu_zmmh11; /* ZMMH 11 */
893 _STRUCT_YMM_REG __fpu_zmmh12; /* ZMMH 12 */
894 _STRUCT_YMM_REG __fpu_zmmh13; /* ZMMH 13 */
895 _STRUCT_YMM_REG __fpu_zmmh14; /* ZMMH 14 */
896 _STRUCT_YMM_REG __fpu_zmmh15; /* ZMMH 15 */
897 _STRUCT_ZMM_REG __fpu_zmm16; /* ZMM 16 */
898 _STRUCT_ZMM_REG __fpu_zmm17; /* ZMM 17 */
899 _STRUCT_ZMM_REG __fpu_zmm18; /* ZMM 18 */
900 _STRUCT_ZMM_REG __fpu_zmm19; /* ZMM 19 */
901 _STRUCT_ZMM_REG __fpu_zmm20; /* ZMM 20 */
902 _STRUCT_ZMM_REG __fpu_zmm21; /* ZMM 21 */
903 _STRUCT_ZMM_REG __fpu_zmm22; /* ZMM 22 */
904 _STRUCT_ZMM_REG __fpu_zmm23; /* ZMM 23 */
905 _STRUCT_ZMM_REG __fpu_zmm24; /* ZMM 24 */
906 _STRUCT_ZMM_REG __fpu_zmm25; /* ZMM 25 */
907 _STRUCT_ZMM_REG __fpu_zmm26; /* ZMM 26 */
908 _STRUCT_ZMM_REG __fpu_zmm27; /* ZMM 27 */
909 _STRUCT_ZMM_REG __fpu_zmm28; /* ZMM 28 */
910 _STRUCT_ZMM_REG __fpu_zmm29; /* ZMM 29 */
911 _STRUCT_ZMM_REG __fpu_zmm30; /* ZMM 30 */
912 _STRUCT_ZMM_REG __fpu_zmm31; /* ZMM 31 */
913};
914#endif /* not RC_HIDE_XNU_J137 */
915
916#else /* !__DARWIN_UNIX03 */
917#define _STRUCT_X86_FLOAT_STATE64 struct x86_float_state64
918_STRUCT_X86_FLOAT_STATE64
919{
920 int fpu_reserved[2];
921 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
922 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
923 __uint8_t fpu_ftw; /* x87 FPU tag word */
924 __uint8_t fpu_rsrv1; /* reserved */
925 __uint16_t fpu_fop; /* x87 FPU Opcode */
926
927 /* x87 FPU Instruction Pointer */
928 __uint32_t fpu_ip; /* offset */
929 __uint16_t fpu_cs; /* Selector */
930
931 __uint16_t fpu_rsrv2; /* reserved */
932
933 /* x87 FPU Instruction Operand(Data) Pointer */
934 __uint32_t fpu_dp; /* offset */
935 __uint16_t fpu_ds; /* Selector */
936
937 __uint16_t fpu_rsrv3; /* reserved */
938 __uint32_t fpu_mxcsr; /* MXCSR Register state */
939 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
940 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
941 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
942 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
943 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
944 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
945 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
946 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
947 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
948 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
949 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
950 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
951 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
952 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
953 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
954 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
955 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
956 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
957 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
958 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
959 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
960 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
961 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
962 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
963 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
964 char fpu_rsrv4[6*16]; /* reserved */
965 int fpu_reserved1;
966};
967
968#define _STRUCT_X86_AVX_STATE64 struct x86_avx_state64
969_STRUCT_X86_AVX_STATE64
970{
971 int fpu_reserved[2];
972 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
973 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
974 __uint8_t fpu_ftw; /* x87 FPU tag word */
975 __uint8_t fpu_rsrv1; /* reserved */
976 __uint16_t fpu_fop; /* x87 FPU Opcode */
977
978 /* x87 FPU Instruction Pointer */
979 __uint32_t fpu_ip; /* offset */
980 __uint16_t fpu_cs; /* Selector */
981
982 __uint16_t fpu_rsrv2; /* reserved */
983
984 /* x87 FPU Instruction Operand(Data) Pointer */
985 __uint32_t fpu_dp; /* offset */
986 __uint16_t fpu_ds; /* Selector */
987
988 __uint16_t fpu_rsrv3; /* reserved */
989 __uint32_t fpu_mxcsr; /* MXCSR Register state */
990 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
991 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
992 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
993 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
994 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
995 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
996 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
997 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
998 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
999 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1000 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1001 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1002 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1003 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1004 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1005 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1006 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1007 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1008 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1009 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1010 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1011 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1012 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1013 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1014 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1015 char fpu_rsrv4[6*16]; /* reserved */
1016 int fpu_reserved1;
1017 char avx_reserved1[64];
1018 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
1019 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
1020 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
1021 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
1022 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
1023 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
1024 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
1025 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
1026 _STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
1027 _STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
1028 _STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
1029 _STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
1030 _STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
1031 _STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
1032 _STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
1033 _STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
1034};
1035
1036#if !defined(RC_HIDE_XNU_J137)
1037#define _STRUCT_X86_AVX512_STATE64 struct x86_avx512_state64
1038_STRUCT_X86_AVX512_STATE64
1039{
1040 int fpu_reserved[2];
1041 _STRUCT_FP_CONTROL fpu_fcw; /* x87 FPU control word */
1042 _STRUCT_FP_STATUS fpu_fsw; /* x87 FPU status word */
1043 __uint8_t fpu_ftw; /* x87 FPU tag word */
1044 __uint8_t fpu_rsrv1; /* reserved */
1045 __uint16_t fpu_fop; /* x87 FPU Opcode */
1046
1047 /* x87 FPU Instruction Pointer */
1048 __uint32_t fpu_ip; /* offset */
1049 __uint16_t fpu_cs; /* Selector */
1050
1051 __uint16_t fpu_rsrv2; /* reserved */
1052
1053 /* x87 FPU Instruction Operand(Data) Pointer */
1054 __uint32_t fpu_dp; /* offset */
1055 __uint16_t fpu_ds; /* Selector */
1056
1057 __uint16_t fpu_rsrv3; /* reserved */
1058 __uint32_t fpu_mxcsr; /* MXCSR Register state */
1059 __uint32_t fpu_mxcsrmask; /* MXCSR mask */
1060 _STRUCT_MMST_REG fpu_stmm0; /* ST0/MM0 */
1061 _STRUCT_MMST_REG fpu_stmm1; /* ST1/MM1 */
1062 _STRUCT_MMST_REG fpu_stmm2; /* ST2/MM2 */
1063 _STRUCT_MMST_REG fpu_stmm3; /* ST3/MM3 */
1064 _STRUCT_MMST_REG fpu_stmm4; /* ST4/MM4 */
1065 _STRUCT_MMST_REG fpu_stmm5; /* ST5/MM5 */
1066 _STRUCT_MMST_REG fpu_stmm6; /* ST6/MM6 */
1067 _STRUCT_MMST_REG fpu_stmm7; /* ST7/MM7 */
1068 _STRUCT_XMM_REG fpu_xmm0; /* XMM 0 */
1069 _STRUCT_XMM_REG fpu_xmm1; /* XMM 1 */
1070 _STRUCT_XMM_REG fpu_xmm2; /* XMM 2 */
1071 _STRUCT_XMM_REG fpu_xmm3; /* XMM 3 */
1072 _STRUCT_XMM_REG fpu_xmm4; /* XMM 4 */
1073 _STRUCT_XMM_REG fpu_xmm5; /* XMM 5 */
1074 _STRUCT_XMM_REG fpu_xmm6; /* XMM 6 */
1075 _STRUCT_XMM_REG fpu_xmm7; /* XMM 7 */
1076 _STRUCT_XMM_REG fpu_xmm8; /* XMM 8 */
1077 _STRUCT_XMM_REG fpu_xmm9; /* XMM 9 */
1078 _STRUCT_XMM_REG fpu_xmm10; /* XMM 10 */
1079 _STRUCT_XMM_REG fpu_xmm11; /* XMM 11 */
1080 _STRUCT_XMM_REG fpu_xmm12; /* XMM 12 */
1081 _STRUCT_XMM_REG fpu_xmm13; /* XMM 13 */
1082 _STRUCT_XMM_REG fpu_xmm14; /* XMM 14 */
1083 _STRUCT_XMM_REG fpu_xmm15; /* XMM 15 */
1084 char fpu_rsrv4[6*16]; /* reserved */
1085 int fpu_reserved1;
1086 char avx_reserved1[64];
1087 _STRUCT_XMM_REG fpu_ymmh0; /* YMMH 0 */
1088 _STRUCT_XMM_REG fpu_ymmh1; /* YMMH 1 */
1089 _STRUCT_XMM_REG fpu_ymmh2; /* YMMH 2 */
1090 _STRUCT_XMM_REG fpu_ymmh3; /* YMMH 3 */
1091 _STRUCT_XMM_REG fpu_ymmh4; /* YMMH 4 */
1092 _STRUCT_XMM_REG fpu_ymmh5; /* YMMH 5 */
1093 _STRUCT_XMM_REG fpu_ymmh6; /* YMMH 6 */
1094 _STRUCT_XMM_REG fpu_ymmh7; /* YMMH 7 */
1095 _STRUCT_XMM_REG fpu_ymmh8; /* YMMH 8 */
1096 _STRUCT_XMM_REG fpu_ymmh9; /* YMMH 9 */
1097 _STRUCT_XMM_REG fpu_ymmh10; /* YMMH 10 */
1098 _STRUCT_XMM_REG fpu_ymmh11; /* YMMH 11 */
1099 _STRUCT_XMM_REG fpu_ymmh12; /* YMMH 12 */
1100 _STRUCT_XMM_REG fpu_ymmh13; /* YMMH 13 */
1101 _STRUCT_XMM_REG fpu_ymmh14; /* YMMH 14 */
1102 _STRUCT_XMM_REG fpu_ymmh15; /* YMMH 15 */
1103 _STRUCT_OPMASK_REG fpu_k0; /* K0 */
1104 _STRUCT_OPMASK_REG fpu_k1; /* K1 */
1105 _STRUCT_OPMASK_REG fpu_k2; /* K2 */
1106 _STRUCT_OPMASK_REG fpu_k3; /* K3 */
1107 _STRUCT_OPMASK_REG fpu_k4; /* K4 */
1108 _STRUCT_OPMASK_REG fpu_k5; /* K5 */
1109 _STRUCT_OPMASK_REG fpu_k6; /* K6 */
1110 _STRUCT_OPMASK_REG fpu_k7; /* K7 */
1111 _STRUCT_YMM_REG fpu_zmmh0; /* ZMMH 0 */
1112 _STRUCT_YMM_REG fpu_zmmh1; /* ZMMH 1 */
1113 _STRUCT_YMM_REG fpu_zmmh2; /* ZMMH 2 */
1114 _STRUCT_YMM_REG fpu_zmmh3; /* ZMMH 3 */
1115 _STRUCT_YMM_REG fpu_zmmh4; /* ZMMH 4 */
1116 _STRUCT_YMM_REG fpu_zmmh5; /* ZMMH 5 */
1117 _STRUCT_YMM_REG fpu_zmmh6; /* ZMMH 6 */
1118 _STRUCT_YMM_REG fpu_zmmh7; /* ZMMH 7 */
1119 _STRUCT_YMM_REG fpu_zmmh8; /* ZMMH 8 */
1120 _STRUCT_YMM_REG fpu_zmmh9; /* ZMMH 9 */
1121 _STRUCT_YMM_REG fpu_zmmh10; /* ZMMH 10 */
1122 _STRUCT_YMM_REG fpu_zmmh11; /* ZMMH 11 */
1123 _STRUCT_YMM_REG fpu_zmmh12; /* ZMMH 12 */
1124 _STRUCT_YMM_REG fpu_zmmh13; /* ZMMH 13 */
1125 _STRUCT_YMM_REG fpu_zmmh14; /* ZMMH 14 */
1126 _STRUCT_YMM_REG fpu_zmmh15; /* ZMMH 15 */
1127 _STRUCT_ZMM_REG fpu_zmm16; /* ZMM 16 */
1128 _STRUCT_ZMM_REG fpu_zmm17; /* ZMM 17 */
1129 _STRUCT_ZMM_REG fpu_zmm18; /* ZMM 18 */
1130 _STRUCT_ZMM_REG fpu_zmm19; /* ZMM 19 */
1131 _STRUCT_ZMM_REG fpu_zmm20; /* ZMM 20 */
1132 _STRUCT_ZMM_REG fpu_zmm21; /* ZMM 21 */
1133 _STRUCT_ZMM_REG fpu_zmm22; /* ZMM 22 */
1134 _STRUCT_ZMM_REG fpu_zmm23; /* ZMM 23 */
1135 _STRUCT_ZMM_REG fpu_zmm24; /* ZMM 24 */
1136 _STRUCT_ZMM_REG fpu_zmm25; /* ZMM 25 */
1137 _STRUCT_ZMM_REG fpu_zmm26; /* ZMM 26 */
1138 _STRUCT_ZMM_REG fpu_zmm27; /* ZMM 27 */
1139 _STRUCT_ZMM_REG fpu_zmm28; /* ZMM 28 */
1140 _STRUCT_ZMM_REG fpu_zmm29; /* ZMM 29 */
1141 _STRUCT_ZMM_REG fpu_zmm30; /* ZMM 30 */
1142 _STRUCT_ZMM_REG fpu_zmm31; /* ZMM 31 */
1143};
1144#endif /* not RC_HIDE_XNU_J137 */
1145
1146#endif /* !__DARWIN_UNIX03 */
1147
1148#if __DARWIN_UNIX03
1149#define _STRUCT_X86_EXCEPTION_STATE64 struct __darwin_x86_exception_state64
1150_STRUCT_X86_EXCEPTION_STATE64
1151{
1152 __uint16_t __trapno;
1153 __uint16_t __cpu;
1154 __uint32_t __err;
1155 __uint64_t __faultvaddr;
1156};
1157#else /* !__DARWIN_UNIX03 */
1158#define _STRUCT_X86_EXCEPTION_STATE64 struct x86_exception_state64
1159_STRUCT_X86_EXCEPTION_STATE64
1160{
1161 __uint16_t trapno;
1162 __uint16_t cpu;
1163 __uint32_t err;
1164 __uint64_t faultvaddr;
1165};
1166#endif /* !__DARWIN_UNIX03 */
1167
1168#if __DARWIN_UNIX03
1169#define _STRUCT_X86_DEBUG_STATE64 struct __darwin_x86_debug_state64
1170_STRUCT_X86_DEBUG_STATE64
1171{
1172 __uint64_t __dr0;
1173 __uint64_t __dr1;
1174 __uint64_t __dr2;
1175 __uint64_t __dr3;
1176 __uint64_t __dr4;
1177 __uint64_t __dr5;
1178 __uint64_t __dr6;
1179 __uint64_t __dr7;
1180};
1181#else /* !__DARWIN_UNIX03 */
1182#define _STRUCT_X86_DEBUG_STATE64 struct x86_debug_state64
1183_STRUCT_X86_DEBUG_STATE64
1184{
1185 __uint64_t dr0;
1186 __uint64_t dr1;
1187 __uint64_t dr2;
1188 __uint64_t dr3;
1189 __uint64_t dr4;
1190 __uint64_t dr5;
1191 __uint64_t dr6;
1192 __uint64_t dr7;
1193};
1194#endif /* !__DARWIN_UNIX03 */
1195
1196#if __DARWIN_UNIX03
1197#define _STRUCT_X86_CPMU_STATE64 struct __darwin_x86_cpmu_state64
1198_STRUCT_X86_CPMU_STATE64
1199{
1200 __uint64_t __ctrs[16];
1201};
1202#else /* __DARWIN_UNIX03 */
1203#define _STRUCT_X86_CPMU_STATE64 struct x86_cpmu_state64
1204_STRUCT_X86_CPMU_STATE64
1205{
1206 __uint64_t ctrs[16];
1207};
1208#endif /* !__DARWIN_UNIX03 */
1209
1210#endif /* _MACH_I386__STRUCTS_H_ */
1211