1/*
2 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28/*
29 * @OSF_COPYRIGHT@
30 */
31
32/*
33 * x86 CPU identification
34 *
35 */
36
37#ifndef _MACHINE_CPUID_H_
38#define _MACHINE_CPUID_H_
39
40#include <sys/appleapiopts.h>
41
42#ifdef __APPLE_API_PRIVATE
43
44#define CPUID_VID_INTEL "GenuineIntel"
45#define CPUID_VID_AMD "AuthenticAMD"
46
47#define CPUID_VMM_ID_VMWARE "VMwareVMware"
48#define CPUID_VMM_ID_PARALLELS "Parallels\0\0\0"
49
50#define CPUID_STRING_UNKNOWN "Unknown CPU Typ"
51
52#define _Bit(n) (1ULL << n)
53#define _HBit(n) (1ULL << ((n)+32))
54
55/*
56 * The CPUID_FEATURE_XXX values define 64-bit values
57 * returned in %ecx:%edx to a CPUID request with %eax of 1:
58 */
59#define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */
60#define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */
61#define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */
62#define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */
63#define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */
64#define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */
65#define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */
66#define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */
67#define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */
68#define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */
69#define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */
70#define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */
71#define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */
72#define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */
73#define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */
74#define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */
75#define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */
76#define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */
77#define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */
78#define CPUID_FEATURE_DS _Bit(21) /* Debug Store */
79#define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */
80#define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */
81#define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */
82#define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */
83#define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */
84#define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */
85#define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */
86#define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */
87#define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */
88
89#define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */
90#define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */
91#define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */
92#define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */
93#define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */
94#define CPUID_FEATURE_VMX _HBit(5) /* VMX */
95#define CPUID_FEATURE_SMX _HBit(6) /* SMX */
96#define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */
97#define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */
98#define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */
99#define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */
100#define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */
101#define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */
102#define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */
103#define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */
104#define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */
105
106#define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */
107#define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */
108#define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */
109#define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */
110#define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */
111#define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */
112#define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */
113#define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */
114#define CPUID_FEATURE_AES _HBit(25) /* AES instructions */
115#define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */
116#define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */
117#define CPUID_FEATURE_AVX1_0 _HBit(28) /* AVX 1.0 instructions */
118#define CPUID_FEATURE_F16C _HBit(29) /* Float16 convert instructions */
119#define CPUID_FEATURE_RDRAND _HBit(30) /* RDRAND instruction */
120#define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */
121
122/*
123 * Leaf 7, subleaf 0 additional features.
124 * Bits returned in %ebx:%ecx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
125 */
126#define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0) /* FS/GS base read/write */
127#define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1) /* TSC thread offset */
128#define CPUID_LEAF7_FEATURE_BMI1 _Bit(3) /* Bit Manipulation Instrs, set 1 */
129#define CPUID_LEAF7_FEATURE_HLE _Bit(4) /* Hardware Lock Elision*/
130#define CPUID_LEAF7_FEATURE_AVX2 _Bit(5) /* AVX2 Instructions */
131#define CPUID_LEAF7_FEATURE_SMEP _Bit(7) /* Supervisor Mode Execute Protect */
132#define CPUID_LEAF7_FEATURE_BMI2 _Bit(8) /* Bit Manipulation Instrs, set 2 */
133#define CPUID_LEAF7_FEATURE_ERMS _Bit(9) /* Enhanced Rep Movsb/Stosb */
134#define CPUID_LEAF7_FEATURE_INVPCID _Bit(10) /* INVPCID intruction, TDB */
135#define CPUID_LEAF7_FEATURE_RTM _Bit(11) /* RTM */
136#define CPUID_LEAF7_FEATURE_RDSEED _Bit(18) /* RDSEED Instruction */
137#define CPUID_LEAF7_FEATURE_ADX _Bit(19) /* ADX Instructions */
138#define CPUID_LEAF7_FEATURE_SMAP _Bit(20) /* Supervisor Mode Access Protect */
139#define CPUID_LEAF7_FEATURE_SGX _Bit(2) /* Software Guard eXtensions */
140#define CPUID_LEAF7_FEATURE_PQM _Bit(12) /* Platform Qos Monitoring */
141#define CPUID_LEAF7_FEATURE_FPU_CSDS _Bit(13) /* FPU CS/DS deprecation */
142#define CPUID_LEAF7_FEATURE_MPX _Bit(14) /* Memory Protection eXtensions */
143#define CPUID_LEAF7_FEATURE_PQE _Bit(15) /* Platform Qos Enforcement */
144#define CPUID_LEAF7_FEATURE_CLFSOPT _Bit(23) /* CLFSOPT */
145#define CPUID_LEAF7_FEATURE_IPT _Bit(25) /* Intel Processor Trace */
146#define CPUID_LEAF7_FEATURE_SHA _Bit(29) /* SHA instructions */
147#if !defined(RC_HIDE_XNU_J137)
148#define CPUID_LEAF7_FEATURE_AVX512F _Bit(16) /* AVX512F instructions */
149#define CPUID_LEAF7_FEATURE_AVX512DQ _Bit(17) /* AVX512DQ instructions */
150#define CPUID_LEAF7_FEATURE_AVX512IFMA _Bit(21) /* AVX512IFMA instructions */
151#define CPUID_LEAF7_FEATURE_AVX512CD _Bit(28) /* AVX512CD instructions */
152#define CPUID_LEAF7_FEATURE_AVX512BW _Bit(30) /* AVX512BW instructions */
153#define CPUID_LEAF7_FEATURE_AVX512VL _Bit(31) /* AVX512VL instructions */
154#endif /* not RC_HIDE_XNU_J137 */
155
156#define CPUID_LEAF7_FEATURE_PREFETCHWT1 _HBit(0)/* Prefetch Write/T1 hint */
157#if !defined(RC_HIDE_XNU_J137)
158#define CPUID_LEAF7_FEATURE_AVX512VBMI _HBit(1)/* AVX512VBMI instructions */
159#endif /* not RC_HIDE_XNU_J137 */
160
161/*
162 * The CPUID_EXTFEATURE_XXX values define 64-bit values
163 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
164 */
165#define CPUID_EXTFEATURE_SYSCALL _Bit(11) /* SYSCALL/sysret */
166#define CPUID_EXTFEATURE_XD _Bit(20) /* eXecute Disable */
167
168#define CPUID_EXTFEATURE_1GBPAGE _Bit(26) /* 1GB pages */
169#define CPUID_EXTFEATURE_RDTSCP _Bit(27) /* RDTSCP */
170#define CPUID_EXTFEATURE_EM64T _Bit(29) /* Extended Mem 64 Technology */
171
172#define CPUID_EXTFEATURE_LAHF _HBit(0) /* LAFH/SAHF instructions */
173#define CPUID_EXTFEATURE_LZCNT _HBit(5) /* LZCNT instruction */
174#define CPUID_EXTFEATURE_PREFETCHW _HBit(8) /* PREFETCHW instruction */
175
176/*
177 * The CPUID_EXTFEATURE_XXX values define 64-bit values
178 * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
179 */
180#define CPUID_EXTFEATURE_TSCI _Bit(8) /* TSC Invariant */
181
182/*
183 * CPUID_X86_64_H_FEATURE_SUBSET and CPUID_X86_64_H_LEAF7_FEATURE_SUBSET
184 * indicate the bitmask of features that must be present before the system
185 * is eligible to run the "x86_64h" "Haswell feature subset" slice.
186 */
187#define CPUID_X86_64_H_FEATURE_SUBSET ( CPUID_FEATURE_FMA | \
188 CPUID_FEATURE_SSE4_2 | \
189 CPUID_FEATURE_MOVBE | \
190 CPUID_FEATURE_POPCNT | \
191 CPUID_FEATURE_AVX1_0 \
192 )
193
194#define CPUID_X86_64_H_EXTFEATURE_SUBSET ( CPUID_EXTFEATURE_LZCNT \
195 )
196
197#define CPUID_X86_64_H_LEAF7_FEATURE_SUBSET ( CPUID_LEAF7_FEATURE_BMI1 | \
198 CPUID_LEAF7_FEATURE_AVX2 | \
199 CPUID_LEAF7_FEATURE_BMI2 \
200 )
201
202#define CPUID_CACHE_SIZE 16 /* Number of descriptor values */
203
204#define CPUID_MWAIT_EXTENSION _Bit(0) /* enumeration of WMAIT extensions */
205#define CPUID_MWAIT_BREAK _Bit(1) /* interrupts are break events */
206
207#define CPUID_MODEL_PENRYN 0x17
208#define CPUID_MODEL_NEHALEM 0x1A
209#define CPUID_MODEL_FIELDS 0x1E /* Lynnfield, Clarksfield */
210#define CPUID_MODEL_DALES 0x1F /* Havendale, Auburndale */
211#define CPUID_MODEL_NEHALEM_EX 0x2E
212#define CPUID_MODEL_DALES_32NM 0x25 /* Clarkdale, Arrandale */
213#define CPUID_MODEL_WESTMERE 0x2C /* Gulftown, Westmere-EP/-WS */
214#define CPUID_MODEL_WESTMERE_EX 0x2F
215#define CPUID_MODEL_SANDYBRIDGE 0x2A
216#define CPUID_MODEL_JAKETOWN 0x2D
217#define CPUID_MODEL_IVYBRIDGE 0x3A
218#define CPUID_MODEL_IVYBRIDGE_EP 0x3E
219#define CPUID_MODEL_CRYSTALWELL 0x46
220#define CPUID_MODEL_HASWELL 0x3C
221#define CPUID_MODEL_HASWELL_EP 0x3F
222#define CPUID_MODEL_HASWELL_ULT 0x45
223#define CPUID_MODEL_BROADWELL 0x3D
224#define CPUID_MODEL_BROADWELL_ULX 0x3D
225#define CPUID_MODEL_BROADWELL_ULT 0x3D
226#define CPUID_MODEL_BRYSTALWELL 0x47
227#define CPUID_MODEL_SKYLAKE 0x4E
228#define CPUID_MODEL_SKYLAKE_ULT 0x4E
229#define CPUID_MODEL_SKYLAKE_ULX 0x4E
230#define CPUID_MODEL_SKYLAKE_DT 0x5E
231#if !defined(RC_HIDE_XNU_J137)
232#define CPUID_MODEL_SKYLAKE_W 0x55
233#endif /* not RC_HIDE_XNU_J137 */
234#define CPUID_MODEL_KABYLAKE 0x8E
235#define CPUID_MODEL_KABYLAKE_ULT 0x8E
236#define CPUID_MODEL_KABYLAKE_ULX 0x8E
237#define CPUID_MODEL_KABYLAKE_DT 0x9E
238
239#define CPUID_VMM_FAMILY_UNKNOWN 0x0
240#define CPUID_VMM_FAMILY_VMWARE 0x1
241#define CPUID_VMM_FAMILY_PARALLELS 0x2
242
243#ifndef ASSEMBLER
244#include <stdint.h>
245#include <mach/mach_types.h>
246#include <kern/kern_types.h>
247#include <mach/machine.h>
248
249
250typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
251static inline void
252cpuid(uint32_t *data)
253{
254 __asm__ volatile ("cpuid"
255 : "=a" (data[eax]),
256 "=b" (data[ebx]),
257 "=c" (data[ecx]),
258 "=d" (data[edx])
259 : "a" (data[eax]),
260 "b" (data[ebx]),
261 "c" (data[ecx]),
262 "d" (data[edx]));
263}
264
265static inline void
266do_cpuid(uint32_t selector, uint32_t *data)
267{
268 __asm__ volatile ("cpuid"
269 : "=a" (data[0]),
270 "=b" (data[1]),
271 "=c" (data[2]),
272 "=d" (data[3])
273 : "a"(selector),
274 "b" (0),
275 "c" (0),
276 "d" (0));
277}
278
279/*
280 * Cache ID descriptor structure, used to parse CPUID leaf 2.
281 * Note: not used in kernel.
282 */
283typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ;
284typedef struct {
285 unsigned char value; /* Descriptor value */
286 cache_type_t type; /* Cache type */
287 unsigned int size; /* Cache size */
288 unsigned int linesize; /* Cache line size */
289#ifdef KERNEL
290 const char *description; /* Cache description */
291#endif /* KERNEL */
292} cpuid_cache_desc_t;
293
294#ifdef KERNEL
295#define CACHE_DESC(value,type,size,linesize,text) \
296 { value, type, size, linesize, text }
297#else
298#define CACHE_DESC(value,type,size,linesize,text) \
299 { value, type, size, linesize }
300#endif /* KERNEL */
301
302/* Monitor/mwait Leaf: */
303typedef struct {
304 uint32_t linesize_min;
305 uint32_t linesize_max;
306 uint32_t extensions;
307 uint32_t sub_Cstates;
308} cpuid_mwait_leaf_t;
309
310/* Thermal and Power Management Leaf: */
311typedef struct {
312 boolean_t sensor;
313 boolean_t dynamic_acceleration;
314 boolean_t invariant_APIC_timer;
315 boolean_t core_power_limits;
316 boolean_t fine_grain_clock_mod;
317 boolean_t package_thermal_intr;
318 uint32_t thresholds;
319 boolean_t ACNT_MCNT;
320 boolean_t hardware_feedback;
321 boolean_t energy_policy;
322} cpuid_thermal_leaf_t;
323
324
325/* XSAVE Feature Leaf: */
326typedef struct {
327 uint32_t extended_state[4]; /* eax .. edx */
328} cpuid_xsave_leaf_t;
329
330
331/* Architectural Performance Monitoring Leaf: */
332typedef struct {
333 uint8_t version;
334 uint8_t number;
335 uint8_t width;
336 uint8_t events_number;
337 uint32_t events;
338 uint8_t fixed_number;
339 uint8_t fixed_width;
340} cpuid_arch_perf_leaf_t;
341
342/* The TSC to Core Crystal (RefCLK) Clock Information leaf */
343typedef struct {
344 uint32_t numerator;
345 uint32_t denominator;
346} cpuid_tsc_leaf_t;
347
348/* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
349typedef struct {
350 char cpuid_vendor[16];
351 char cpuid_brand_string[48];
352 const char *cpuid_model_string;
353
354 cpu_type_t cpuid_type; /* this is *not* a cpu_type_t in our <mach/machine.h> */
355 uint8_t cpuid_family;
356 uint8_t cpuid_model;
357 uint8_t cpuid_extmodel;
358 uint8_t cpuid_extfamily;
359 uint8_t cpuid_stepping;
360 uint64_t cpuid_features;
361 uint64_t cpuid_extfeatures;
362 uint32_t cpuid_signature;
363 uint8_t cpuid_brand;
364 uint8_t cpuid_processor_flag;
365
366 uint32_t cache_size[LCACHE_MAX];
367 uint32_t cache_linesize;
368
369 uint8_t cache_info[64]; /* list of cache descriptors */
370
371 uint32_t cpuid_cores_per_package;
372 uint32_t cpuid_logical_per_package;
373 uint32_t cache_sharing[LCACHE_MAX];
374 uint32_t cache_partitions[LCACHE_MAX];
375
376 cpu_type_t cpuid_cpu_type; /* <mach/machine.h> */
377 cpu_subtype_t cpuid_cpu_subtype; /* <mach/machine.h> */
378
379 /* Per-vendor info */
380 cpuid_mwait_leaf_t cpuid_mwait_leaf;
381#define cpuid_mwait_linesize_max cpuid_mwait_leaf.linesize_max
382#define cpuid_mwait_linesize_min cpuid_mwait_leaf.linesize_min
383#define cpuid_mwait_extensions cpuid_mwait_leaf.extensions
384#define cpuid_mwait_sub_Cstates cpuid_mwait_leaf.sub_Cstates
385 cpuid_thermal_leaf_t cpuid_thermal_leaf;
386 cpuid_arch_perf_leaf_t cpuid_arch_perf_leaf;
387 uint32_t unused[4]; /* cpuid_xsave_leaf */
388
389 /* Cache details: */
390 uint32_t cpuid_cache_linesize;
391 uint32_t cpuid_cache_L2_associativity;
392 uint32_t cpuid_cache_size;
393
394 /* Virtual and physical address aize: */
395 uint32_t cpuid_address_bits_physical;
396 uint32_t cpuid_address_bits_virtual;
397
398 uint32_t cpuid_microcode_version;
399
400 /* Numbers of tlbs per processor [i|d, small|large, level0|level1] */
401 uint32_t cpuid_tlb[2][2][2];
402 #define TLB_INST 0
403 #define TLB_DATA 1
404 #define TLB_SMALL 0
405 #define TLB_LARGE 1
406 uint32_t cpuid_stlb;
407
408 uint32_t core_count;
409 uint32_t thread_count;
410
411 /* Max leaf ids available from CPUID */
412 uint32_t cpuid_max_basic;
413 uint32_t cpuid_max_ext;
414
415 /* Family-specific info links */
416 uint32_t cpuid_cpufamily;
417 cpuid_mwait_leaf_t *cpuid_mwait_leafp;
418 cpuid_thermal_leaf_t *cpuid_thermal_leafp;
419 cpuid_arch_perf_leaf_t *cpuid_arch_perf_leafp;
420 cpuid_xsave_leaf_t *cpuid_xsave_leafp;
421 uint64_t cpuid_leaf7_features;
422 cpuid_tsc_leaf_t cpuid_tsc_leaf;
423 cpuid_xsave_leaf_t cpuid_xsave_leaf[2];
424} i386_cpu_info_t;
425
426#ifdef MACH_KERNEL_PRIVATE
427typedef struct {
428 char cpuid_vmm_vendor[16];
429 uint32_t cpuid_vmm_family;
430 uint32_t cpuid_vmm_bus_frequency;
431 uint32_t cpuid_vmm_tsc_frequency;
432} i386_vmm_info_t;
433#endif
434
435#ifdef __cplusplus
436extern "C" {
437#endif
438
439/*
440 * External declarations
441 */
442extern cpu_type_t cpuid_cputype(void);
443extern cpu_subtype_t cpuid_cpusubtype(void);
444extern void cpuid_cpu_display(const char *);
445extern void cpuid_feature_display(const char *);
446extern void cpuid_extfeature_display(const char *);
447extern char * cpuid_get_feature_names(uint64_t, char *, unsigned);
448extern char * cpuid_get_extfeature_names(uint64_t, char *, unsigned);
449extern char * cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);
450
451extern uint64_t cpuid_features(void);
452extern uint64_t cpuid_extfeatures(void);
453extern uint64_t cpuid_leaf7_features(void);
454extern uint32_t cpuid_family(void);
455extern uint32_t cpuid_cpufamily(void);
456
457extern i386_cpu_info_t *cpuid_info(void);
458extern void cpuid_set_info(void);
459
460#ifdef MACH_KERNEL_PRIVATE
461extern boolean_t cpuid_vmm_present(void);
462extern i386_vmm_info_t *cpuid_vmm_info(void);
463extern uint32_t cpuid_vmm_family(void);
464#endif
465
466#ifdef __cplusplus
467}
468#endif
469
470#endif /* ASSEMBLER */
471
472#endif /* __APPLE_API_PRIVATE */
473#endif /* _MACHINE_CPUID_H_ */
474