1/* Data structure for x86 CPU features.
2 Copyright (C) 2020-2023 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <https://www.gnu.org/licenses/>. */
18
19#ifndef _PRIVATE_CPU_FEATURES_H
20#define _PRIVATE_CPU_FEATURES_H 1
21
22#ifdef _CPU_FEATURES_H
23# error this should be impossible
24#endif
25
26/* Get data structures without inline functions. */
27#define _SYS_PLATFORM_X86_H
28#include <bits/platform/x86.h>
29
30enum
31{
32 CPUID_INDEX_MAX = CPUID_INDEX_14_ECX_0 + 1
33};
34
35enum
36{
37 /* The integer bit array index for the first set of preferred feature
38 bits. */
39 PREFERRED_FEATURE_INDEX_1 = 0,
40 /* The current maximum size of the feature integer bit array. */
41 PREFERRED_FEATURE_INDEX_MAX
42};
43
44/* Only used directly in cpu-features.c. */
45#define CPU_FEATURE_SET(ptr, name) \
46 ptr->features[index_cpu_##name].active.reg_##name |= bit_cpu_##name;
47#define CPU_FEATURE_UNSET(ptr, name) \
48 ptr->features[index_cpu_##name].active.reg_##name &= ~bit_cpu_##name;
49#define CPU_FEATURE_SET_ACTIVE(ptr, name) \
50 ptr->features[index_cpu_##name].active.reg_##name \
51 |= ptr->features[index_cpu_##name].cpuid.reg_##name & bit_cpu_##name;
52#define CPU_FEATURE_PREFERRED_P(ptr, name) \
53 ((ptr->preferred[index_arch_##name] & bit_arch_##name) != 0)
54
55#define CPU_FEATURE_CHECK_P(ptr, name, check) \
56 ((ptr->features[index_cpu_##name].check.reg_##name \
57 & bit_cpu_##name) != 0)
58#define CPU_FEATURE_PRESENT_P(ptr, name) \
59 CPU_FEATURE_CHECK_P (ptr, name, cpuid)
60#define CPU_FEATURE_ACTIVE_P(ptr, name) \
61 CPU_FEATURE_CHECK_P (ptr, name, active)
62#define CPU_FEATURE_CPU_P(ptr, name) \
63 CPU_FEATURE_PRESENT_P (ptr, name)
64#define CPU_FEATURE_USABLE_P(ptr, name) \
65 CPU_FEATURE_ACTIVE_P (ptr, name)
66
67/* HAS_CPU_FEATURE evaluates to true if CPU supports the feature. */
68#define HAS_CPU_FEATURE(name) \
69 CPU_FEATURE_CPU_P (__get_cpu_features (), name)
70/* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
71#define CPU_FEATURE_USABLE(name) \
72 CPU_FEATURE_USABLE_P (__get_cpu_features (), name)
73/* CPU_FEATURE_PREFER evaluates to true if we prefer the feature at
74 runtime. */
75#define CPU_FEATURE_PREFERRED(name) \
76 CPU_FEATURE_PREFERRED_P(__get_cpu_features (), name)
77
78#define CPU_FEATURES_CPU_P(ptr, name) \
79 CPU_FEATURE_CPU_P (ptr, name)
80#define CPU_FEATURES_ARCH_P(ptr, name) \
81 CPU_FEATURE_PREFERRED_P (ptr, name)
82#define HAS_ARCH_FEATURE(name) \
83 CPU_FEATURE_PREFERRED (name)
84
85/* CPU features. */
86
87/* CPUID_INDEX_1. */
88
89/* ECX. */
90#define bit_cpu_SSE3 (1u << 0)
91#define bit_cpu_PCLMULQDQ (1u << 1)
92#define bit_cpu_DTES64 (1u << 2)
93#define bit_cpu_MONITOR (1u << 3)
94#define bit_cpu_DS_CPL (1u << 4)
95#define bit_cpu_VMX (1u << 5)
96#define bit_cpu_SMX (1u << 6)
97#define bit_cpu_EIST (1u << 7)
98#define bit_cpu_TM2 (1u << 8)
99#define bit_cpu_SSSE3 (1u << 9)
100#define bit_cpu_CNXT_ID (1u << 10)
101#define bit_cpu_SDBG (1u << 11)
102#define bit_cpu_FMA (1u << 12)
103#define bit_cpu_CMPXCHG16B (1u << 13)
104#define bit_cpu_XTPRUPDCTRL (1u << 14)
105#define bit_cpu_PDCM (1u << 15)
106#define bit_cpu_INDEX_1_ECX_16 (1u << 16)
107#define bit_cpu_PCID (1u << 17)
108#define bit_cpu_DCA (1u << 18)
109#define bit_cpu_SSE4_1 (1u << 19)
110#define bit_cpu_SSE4_2 (1u << 20)
111#define bit_cpu_X2APIC (1u << 21)
112#define bit_cpu_MOVBE (1u << 22)
113#define bit_cpu_POPCNT (1u << 23)
114#define bit_cpu_TSC_DEADLINE (1u << 24)
115#define bit_cpu_AES (1u << 25)
116#define bit_cpu_XSAVE (1u << 26)
117#define bit_cpu_OSXSAVE (1u << 27)
118#define bit_cpu_AVX (1u << 28)
119#define bit_cpu_F16C (1u << 29)
120#define bit_cpu_RDRAND (1u << 30)
121#define bit_cpu_INDEX_1_ECX_31 (1u << 31)
122
123/* EDX. */
124#define bit_cpu_FPU (1u << 0)
125#define bit_cpu_VME (1u << 1)
126#define bit_cpu_DE (1u << 2)
127#define bit_cpu_PSE (1u << 3)
128#define bit_cpu_TSC (1u << 4)
129#define bit_cpu_MSR (1u << 5)
130#define bit_cpu_PAE (1u << 6)
131#define bit_cpu_MCE (1u << 7)
132#define bit_cpu_CX8 (1u << 8)
133#define bit_cpu_APIC (1u << 9)
134#define bit_cpu_INDEX_1_EDX_10 (1u << 10)
135#define bit_cpu_SEP (1u << 11)
136#define bit_cpu_MTRR (1u << 12)
137#define bit_cpu_PGE (1u << 13)
138#define bit_cpu_MCA (1u << 14)
139#define bit_cpu_CMOV (1u << 15)
140#define bit_cpu_PAT (1u << 16)
141#define bit_cpu_PSE_36 (1u << 17)
142#define bit_cpu_PSN (1u << 18)
143#define bit_cpu_CLFSH (1u << 19)
144#define bit_cpu_INDEX_1_EDX_20 (1u << 20)
145#define bit_cpu_DS (1u << 21)
146#define bit_cpu_ACPI (1u << 22)
147#define bit_cpu_MMX (1u << 23)
148#define bit_cpu_FXSR (1u << 24)
149#define bit_cpu_SSE (1u << 25)
150#define bit_cpu_SSE2 (1u << 26)
151#define bit_cpu_SS (1u << 27)
152#define bit_cpu_HTT (1u << 28)
153#define bit_cpu_TM (1u << 29)
154#define bit_cpu_INDEX_1_EDX_30 (1u << 30)
155#define bit_cpu_PBE (1u << 31)
156
157/* CPUID_INDEX_7. */
158
159/* EBX. */
160#define bit_cpu_FSGSBASE (1u << 0)
161#define bit_cpu_TSC_ADJUST (1u << 1)
162#define bit_cpu_SGX (1u << 2)
163#define bit_cpu_BMI1 (1u << 3)
164#define bit_cpu_HLE (1u << 4)
165#define bit_cpu_AVX2 (1u << 5)
166#define bit_cpu_INDEX_7_EBX_6 (1u << 6)
167#define bit_cpu_SMEP (1u << 7)
168#define bit_cpu_BMI2 (1u << 8)
169#define bit_cpu_ERMS (1u << 9)
170#define bit_cpu_INVPCID (1u << 10)
171#define bit_cpu_RTM (1u << 11)
172#define bit_cpu_RDT_M (1u << 12)
173#define bit_cpu_DEPR_FPU_CS_DS (1u << 13)
174#define bit_cpu_MPX (1u << 14)
175#define bit_cpu_RDT_A (1u << 15)
176#define bit_cpu_AVX512F (1u << 16)
177#define bit_cpu_AVX512DQ (1u << 17)
178#define bit_cpu_RDSEED (1u << 18)
179#define bit_cpu_ADX (1u << 19)
180#define bit_cpu_SMAP (1u << 20)
181#define bit_cpu_AVX512_IFMA (1u << 21)
182#define bit_cpu_INDEX_7_EBX_22 (1u << 22)
183#define bit_cpu_CLFLUSHOPT (1u << 23)
184#define bit_cpu_CLWB (1u << 24)
185#define bit_cpu_TRACE (1u << 25)
186#define bit_cpu_AVX512PF (1u << 26)
187#define bit_cpu_AVX512ER (1u << 27)
188#define bit_cpu_AVX512CD (1u << 28)
189#define bit_cpu_SHA (1u << 29)
190#define bit_cpu_AVX512BW (1u << 30)
191#define bit_cpu_AVX512VL (1u << 31)
192
193/* ECX. */
194#define bit_cpu_PREFETCHWT1 (1u << 0)
195#define bit_cpu_AVX512_VBMI (1u << 1)
196#define bit_cpu_UMIP (1u << 2)
197#define bit_cpu_PKU (1u << 3)
198#define bit_cpu_OSPKE (1u << 4)
199#define bit_cpu_WAITPKG (1u << 5)
200#define bit_cpu_AVX512_VBMI2 (1u << 6)
201#define bit_cpu_SHSTK (1u << 7)
202#define bit_cpu_GFNI (1u << 8)
203#define bit_cpu_VAES (1u << 9)
204#define bit_cpu_VPCLMULQDQ (1u << 10)
205#define bit_cpu_AVX512_VNNI (1u << 11)
206#define bit_cpu_AVX512_BITALG (1u << 12)
207#define bit_cpu_INDEX_7_ECX_13 (1u << 13)
208#define bit_cpu_AVX512_VPOPCNTDQ (1u << 14)
209#define bit_cpu_INDEX_7_ECX_15 (1u << 15)
210#define bit_cpu_INDEX_7_ECX_16 (1u << 16)
211/* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX
212 instructions in 64-bit mode. */
213#define bit_cpu_RDPID (1u << 22)
214#define bit_cpu_KL (1u << 23)
215#define bit_cpu_INDEX_7_ECX_24 (1u << 24)
216#define bit_cpu_CLDEMOTE (1u << 25)
217#define bit_cpu_INDEX_7_ECX_26 (1u << 26)
218#define bit_cpu_MOVDIRI (1u << 27)
219#define bit_cpu_MOVDIR64B (1u << 28)
220#define bit_cpu_ENQCMD (1u << 29)
221#define bit_cpu_SGX_LC (1u << 30)
222#define bit_cpu_PKS (1u << 31)
223
224/* EDX. */
225#define bit_cpu_INDEX_7_EDX_0 (1u << 0)
226#define bit_cpu_INDEX_7_EDX_1 (1u << 1)
227#define bit_cpu_AVX512_4VNNIW (1u << 2)
228#define bit_cpu_AVX512_4FMAPS (1u << 3)
229#define bit_cpu_FSRM (1u << 4)
230#define bit_cpu_UINTR (1u << 5)
231#define bit_cpu_INDEX_7_EDX_6 (1u << 6)
232#define bit_cpu_INDEX_7_EDX_7 (1u << 7)
233#define bit_cpu_AVX512_VP2INTERSECT (1u << 8)
234#define bit_cpu_INDEX_7_EDX_9 (1u << 9)
235#define bit_cpu_MD_CLEAR (1u << 10)
236#define bit_cpu_RTM_ALWAYS_ABORT (1u << 11)
237#define bit_cpu_INDEX_7_EDX_12 (1u << 12)
238#define bit_cpu_INDEX_7_EDX_13 (1u << 13)
239#define bit_cpu_SERIALIZE (1u << 14)
240#define bit_cpu_HYBRID (1u << 15)
241#define bit_cpu_TSXLDTRK (1u << 16)
242#define bit_cpu_INDEX_7_EDX_17 (1u << 17)
243#define bit_cpu_PCONFIG (1u << 18)
244#define bit_cpu_INDEX_7_EDX_19 (1u << 19)
245#define bit_cpu_IBT (1u << 20)
246#define bit_cpu_INDEX_7_EDX_21 (1u << 21)
247#define bit_cpu_AMX_BF16 (1u << 22)
248#define bit_cpu_AVX512_FP16 (1u << 23)
249#define bit_cpu_AMX_TILE (1u << 24)
250#define bit_cpu_AMX_INT8 (1u << 25)
251#define bit_cpu_IBRS_IBPB (1u << 26)
252#define bit_cpu_STIBP (1u << 27)
253#define bit_cpu_L1D_FLUSH (1u << 28)
254#define bit_cpu_ARCH_CAPABILITIES (1u << 29)
255#define bit_cpu_CORE_CAPABILITIES (1u << 30)
256#define bit_cpu_SSBD (1u << 31)
257
258/* CPUID_INDEX_80000001. */
259
260/* ECX. */
261#define bit_cpu_LAHF64_SAHF64 (1u << 0)
262#define bit_cpu_SVM (1u << 2)
263#define bit_cpu_LZCNT (1u << 5)
264#define bit_cpu_SSE4A (1u << 6)
265#define bit_cpu_PREFETCHW (1u << 8)
266#define bit_cpu_XOP (1u << 11)
267#define bit_cpu_LWP (1u << 15)
268#define bit_cpu_FMA4 (1u << 16)
269#define bit_cpu_TBM (1u << 21)
270
271/* EDX. */
272#define bit_cpu_SYSCALL_SYSRET (1u << 11)
273#define bit_cpu_NX (1u << 20)
274#define bit_cpu_PAGE1GB (1u << 26)
275#define bit_cpu_RDTSCP (1u << 27)
276#define bit_cpu_LM (1u << 29)
277
278/* CPUID_INDEX_D_ECX_1. */
279
280/* EAX. */
281#define bit_cpu_XSAVEOPT (1u << 0)
282#define bit_cpu_XSAVEC (1u << 1)
283#define bit_cpu_XGETBV_ECX_1 (1u << 2)
284#define bit_cpu_XSAVES (1u << 3)
285#define bit_cpu_XFD (1u << 4)
286
287/* CPUID_INDEX_80000007. */
288
289/* EDX. */
290#define bit_cpu_INVARIANT_TSC (1u << 8)
291
292/* CPUID_INDEX_80000008. */
293
294/* EBX. */
295#define bit_cpu_WBNOINVD (1u << 9)
296#define bit_cpu_AMD_IBPB (1u << 12)
297#define bit_cpu_AMD_IBRS (1u << 14)
298#define bit_cpu_AMD_STIBP (1u << 15)
299#define bit_cpu_AMD_SSBD (1u << 24)
300#define bit_cpu_AMD_VIRT_SSBD (1u << 25)
301
302/* CPUID_INDEX_7_ECX_1. */
303
304/* EAX. */
305#define bit_cpu_RAO_INT (1u << 3)
306#define bit_cpu_AVX_VNNI (1u << 4)
307#define bit_cpu_AVX512_BF16 (1u << 5)
308#define bit_cpu_CMPCCXADD (1u << 7)
309#define bit_cpu_FZLRM (1u << 10)
310#define bit_cpu_FSRS (1u << 11)
311#define bit_cpu_FSRCS (1u << 12)
312#define bit_cpu_AMX_FP16 (1u << 21)
313#define bit_cpu_HRESET (1u << 22)
314#define bit_cpu_AVX_IFMA (1u << 23)
315#define bit_cpu_LAM (1u << 26)
316
317/* EDX. */
318#define bit_cpu_AVX_VNNI_INT8 (1u << 4)
319#define bit_cpu_AVX_NE_CONVERT (1u << 5)
320#define bit_cpu_AMX_COMPLEX (1u << 8)
321#define bit_cpu_PREFETCHI (1u << 14)
322#define bit_cpu_APX_F (1u << 21)
323
324/* CPUID_INDEX_19. */
325
326/* EBX. */
327#define bit_cpu_AESKLE (1u << 0)
328#define bit_cpu_WIDE_KL (1u << 2)
329
330/* CPUID_INDEX_14_ECX_0. */
331
332/* EBX. */
333#define bit_cpu_PTWRITE (1u << 4)
334
335/* CPUID_INDEX_1. */
336
337/* ECX. */
338#define index_cpu_SSE3 CPUID_INDEX_1
339#define index_cpu_PCLMULQDQ CPUID_INDEX_1
340#define index_cpu_DTES64 CPUID_INDEX_1
341#define index_cpu_MONITOR CPUID_INDEX_1
342#define index_cpu_DS_CPL CPUID_INDEX_1
343#define index_cpu_VMX CPUID_INDEX_1
344#define index_cpu_SMX CPUID_INDEX_1
345#define index_cpu_EIST CPUID_INDEX_1
346#define index_cpu_TM2 CPUID_INDEX_1
347#define index_cpu_SSSE3 CPUID_INDEX_1
348#define index_cpu_CNXT_ID CPUID_INDEX_1
349#define index_cpu_SDBG CPUID_INDEX_1
350#define index_cpu_FMA CPUID_INDEX_1
351#define index_cpu_CMPXCHG16B CPUID_INDEX_1
352#define index_cpu_XTPRUPDCTRL CPUID_INDEX_1
353#define index_cpu_PDCM CPUID_INDEX_1
354#define index_cpu_INDEX_1_ECX_16 CPUID_INDEX_1
355#define index_cpu_PCID CPUID_INDEX_1
356#define index_cpu_DCA CPUID_INDEX_1
357#define index_cpu_SSE4_1 CPUID_INDEX_1
358#define index_cpu_SSE4_2 CPUID_INDEX_1
359#define index_cpu_X2APIC CPUID_INDEX_1
360#define index_cpu_MOVBE CPUID_INDEX_1
361#define index_cpu_POPCNT CPUID_INDEX_1
362#define index_cpu_TSC_DEADLINE CPUID_INDEX_1
363#define index_cpu_AES CPUID_INDEX_1
364#define index_cpu_XSAVE CPUID_INDEX_1
365#define index_cpu_OSXSAVE CPUID_INDEX_1
366#define index_cpu_AVX CPUID_INDEX_1
367#define index_cpu_F16C CPUID_INDEX_1
368#define index_cpu_RDRAND CPUID_INDEX_1
369#define index_cpu_INDEX_1_ECX_31 CPUID_INDEX_1
370
371/* ECX. */
372#define index_cpu_FPU CPUID_INDEX_1
373#define index_cpu_VME CPUID_INDEX_1
374#define index_cpu_DE CPUID_INDEX_1
375#define index_cpu_PSE CPUID_INDEX_1
376#define index_cpu_TSC CPUID_INDEX_1
377#define index_cpu_MSR CPUID_INDEX_1
378#define index_cpu_PAE CPUID_INDEX_1
379#define index_cpu_MCE CPUID_INDEX_1
380#define index_cpu_CX8 CPUID_INDEX_1
381#define index_cpu_APIC CPUID_INDEX_1
382#define index_cpu_INDEX_1_EDX_10 CPUID_INDEX_1
383#define index_cpu_SEP CPUID_INDEX_1
384#define index_cpu_MTRR CPUID_INDEX_1
385#define index_cpu_PGE CPUID_INDEX_1
386#define index_cpu_MCA CPUID_INDEX_1
387#define index_cpu_CMOV CPUID_INDEX_1
388#define index_cpu_PAT CPUID_INDEX_1
389#define index_cpu_PSE_36 CPUID_INDEX_1
390#define index_cpu_PSN CPUID_INDEX_1
391#define index_cpu_CLFSH CPUID_INDEX_1
392#define index_cpu_INDEX_1_EDX_20 CPUID_INDEX_1
393#define index_cpu_DS CPUID_INDEX_1
394#define index_cpu_ACPI CPUID_INDEX_1
395#define index_cpu_MMX CPUID_INDEX_1
396#define index_cpu_FXSR CPUID_INDEX_1
397#define index_cpu_SSE CPUID_INDEX_1
398#define index_cpu_SSE2 CPUID_INDEX_1
399#define index_cpu_SS CPUID_INDEX_1
400#define index_cpu_HTT CPUID_INDEX_1
401#define index_cpu_TM CPUID_INDEX_1
402#define index_cpu_INDEX_1_EDX_30 CPUID_INDEX_1
403#define index_cpu_PBE CPUID_INDEX_1
404
405/* CPUID_INDEX_7. */
406
407/* EBX. */
408#define index_cpu_FSGSBASE CPUID_INDEX_7
409#define index_cpu_TSC_ADJUST CPUID_INDEX_7
410#define index_cpu_SGX CPUID_INDEX_7
411#define index_cpu_BMI1 CPUID_INDEX_7
412#define index_cpu_HLE CPUID_INDEX_7
413#define index_cpu_AVX2 CPUID_INDEX_7
414#define index_cpu_INDEX_7_EBX_6 CPUID_INDEX_7
415#define index_cpu_SMEP CPUID_INDEX_7
416#define index_cpu_BMI2 CPUID_INDEX_7
417#define index_cpu_ERMS CPUID_INDEX_7
418#define index_cpu_INVPCID CPUID_INDEX_7
419#define index_cpu_RTM CPUID_INDEX_7
420#define index_cpu_RDT_M CPUID_INDEX_7
421#define index_cpu_DEPR_FPU_CS_DS CPUID_INDEX_7
422#define index_cpu_MPX CPUID_INDEX_7
423#define index_cpu_RDT_A CPUID_INDEX_7
424#define index_cpu_AVX512F CPUID_INDEX_7
425#define index_cpu_AVX512DQ CPUID_INDEX_7
426#define index_cpu_RDSEED CPUID_INDEX_7
427#define index_cpu_ADX CPUID_INDEX_7
428#define index_cpu_SMAP CPUID_INDEX_7
429#define index_cpu_AVX512_IFMA CPUID_INDEX_7
430#define index_cpu_INDEX_7_EBX_22 CPUID_INDEX_7
431#define index_cpu_CLFLUSHOPT CPUID_INDEX_7
432#define index_cpu_CLWB CPUID_INDEX_7
433#define index_cpu_TRACE CPUID_INDEX_7
434#define index_cpu_AVX512PF CPUID_INDEX_7
435#define index_cpu_AVX512ER CPUID_INDEX_7
436#define index_cpu_AVX512CD CPUID_INDEX_7
437#define index_cpu_SHA CPUID_INDEX_7
438#define index_cpu_AVX512BW CPUID_INDEX_7
439#define index_cpu_AVX512VL CPUID_INDEX_7
440
441/* ECX. */
442#define index_cpu_PREFETCHWT1 CPUID_INDEX_7
443#define index_cpu_AVX512_VBMI CPUID_INDEX_7
444#define index_cpu_UMIP CPUID_INDEX_7
445#define index_cpu_PKU CPUID_INDEX_7
446#define index_cpu_OSPKE CPUID_INDEX_7
447#define index_cpu_WAITPKG CPUID_INDEX_7
448#define index_cpu_AVX512_VBMI2 CPUID_INDEX_7
449#define index_cpu_SHSTK CPUID_INDEX_7
450#define index_cpu_GFNI CPUID_INDEX_7
451#define index_cpu_VAES CPUID_INDEX_7
452#define index_cpu_VPCLMULQDQ CPUID_INDEX_7
453#define index_cpu_AVX512_VNNI CPUID_INDEX_7
454#define index_cpu_AVX512_BITALG CPUID_INDEX_7
455#define index_cpu_INDEX_7_ECX_13 CPUID_INDEX_7
456#define index_cpu_AVX512_VPOPCNTDQ CPUID_INDEX_7
457#define index_cpu_INDEX_7_ECX_15 CPUID_INDEX_7
458#define index_cpu_INDEX_7_ECX_16 CPUID_INDEX_7
459#define index_cpu_RDPID CPUID_INDEX_7
460#define index_cpu_KL CPUID_INDEX_7
461#define index_cpu_INDEX_7_ECX_24 CPUID_INDEX_7
462#define index_cpu_CLDEMOTE CPUID_INDEX_7
463#define index_cpu_INDEX_7_ECX_26 CPUID_INDEX_7
464#define index_cpu_MOVDIRI CPUID_INDEX_7
465#define index_cpu_MOVDIR64B CPUID_INDEX_7
466#define index_cpu_ENQCMD CPUID_INDEX_7
467#define index_cpu_SGX_LC CPUID_INDEX_7
468#define index_cpu_PKS CPUID_INDEX_7
469
470/* EDX. */
471#define index_cpu_INDEX_7_EDX_0 CPUID_INDEX_7
472#define index_cpu_INDEX_7_EDX_1 CPUID_INDEX_7
473#define index_cpu_AVX512_4VNNIW CPUID_INDEX_7
474#define index_cpu_AVX512_4FMAPS CPUID_INDEX_7
475#define index_cpu_FSRM CPUID_INDEX_7
476#define index_cpu_UINTR CPUID_INDEX_7
477#define index_cpu_INDEX_7_EDX_6 CPUID_INDEX_7
478#define index_cpu_INDEX_7_EDX_7 CPUID_INDEX_7
479#define index_cpu_AVX512_VP2INTERSECT CPUID_INDEX_7
480#define index_cpu_INDEX_7_EDX_9 CPUID_INDEX_7
481#define index_cpu_MD_CLEAR CPUID_INDEX_7
482#define index_cpu_RTM_ALWAYS_ABORT CPUID_INDEX_7
483#define index_cpu_INDEX_7_EDX_12 CPUID_INDEX_7
484#define index_cpu_INDEX_7_EDX_13 CPUID_INDEX_7
485#define index_cpu_SERIALIZE CPUID_INDEX_7
486#define index_cpu_HYBRID CPUID_INDEX_7
487#define index_cpu_TSXLDTRK CPUID_INDEX_7
488#define index_cpu_INDEX_7_EDX_17 CPUID_INDEX_7
489#define index_cpu_PCONFIG CPUID_INDEX_7
490#define index_cpu_INDEX_7_EDX_19 CPUID_INDEX_7
491#define index_cpu_IBT CPUID_INDEX_7
492#define index_cpu_INDEX_7_EDX_21 CPUID_INDEX_7
493#define index_cpu_AMX_BF16 CPUID_INDEX_7
494#define index_cpu_AVX512_FP16 CPUID_INDEX_7
495#define index_cpu_AMX_TILE CPUID_INDEX_7
496#define index_cpu_AMX_INT8 CPUID_INDEX_7
497#define index_cpu_IBRS_IBPB CPUID_INDEX_7
498#define index_cpu_STIBP CPUID_INDEX_7
499#define index_cpu_L1D_FLUSH CPUID_INDEX_7
500#define index_cpu_ARCH_CAPABILITIES CPUID_INDEX_7
501#define index_cpu_CORE_CAPABILITIES CPUID_INDEX_7
502#define index_cpu_SSBD CPUID_INDEX_7
503
504/* CPUID_INDEX_80000001. */
505
506/* ECX. */
507#define index_cpu_LAHF64_SAHF64 CPUID_INDEX_80000001
508#define index_cpu_SVM CPUID_INDEX_80000001
509#define index_cpu_LZCNT CPUID_INDEX_80000001
510#define index_cpu_SSE4A CPUID_INDEX_80000001
511#define index_cpu_PREFETCHW CPUID_INDEX_80000001
512#define index_cpu_XOP CPUID_INDEX_80000001
513#define index_cpu_LWP CPUID_INDEX_80000001
514#define index_cpu_FMA4 CPUID_INDEX_80000001
515#define index_cpu_TBM CPUID_INDEX_80000001
516
517/* EDX. */
518#define index_cpu_SYSCALL_SYSRET CPUID_INDEX_80000001
519#define index_cpu_NX CPUID_INDEX_80000001
520#define index_cpu_PAGE1GB CPUID_INDEX_80000001
521#define index_cpu_RDTSCP CPUID_INDEX_80000001
522#define index_cpu_LM CPUID_INDEX_80000001
523
524/* CPUID_INDEX_D_ECX_1. */
525
526/* EAX. */
527#define index_cpu_XSAVEOPT CPUID_INDEX_D_ECX_1
528#define index_cpu_XSAVEC CPUID_INDEX_D_ECX_1
529#define index_cpu_XGETBV_ECX_1 CPUID_INDEX_D_ECX_1
530#define index_cpu_XSAVES CPUID_INDEX_D_ECX_1
531#define index_cpu_XFD CPUID_INDEX_D_ECX_1
532
533/* CPUID_INDEX_80000007. */
534
535/* EDX. */
536#define index_cpu_INVARIANT_TSC CPUID_INDEX_80000007
537
538/* CPUID_INDEX_80000008. */
539
540/* EBX. */
541#define index_cpu_WBNOINVD CPUID_INDEX_80000008
542#define index_cpu_AMD_IBPB CPUID_INDEX_80000008
543#define index_cpu_AMD_IBRS CPUID_INDEX_80000008
544#define index_cpu_AMD_STIBP CPUID_INDEX_80000008
545#define index_cpu_AMD_SSBD CPUID_INDEX_80000008
546#define index_cpu_AMD_VIRT_SSBD CPUID_INDEX_80000008
547
548/* CPUID_INDEX_7_ECX_1. */
549
550/* EAX. */
551#define index_cpu_RAO_INT CPUID_INDEX_7_ECX_1
552#define index_cpu_AVX_VNNI CPUID_INDEX_7_ECX_1
553#define index_cpu_AVX512_BF16 CPUID_INDEX_7_ECX_1
554#define index_cpu_CMPCCXADD CPUID_INDEX_7_ECX_1
555#define index_cpu_FZLRM CPUID_INDEX_7_ECX_1
556#define index_cpu_FSRS CPUID_INDEX_7_ECX_1
557#define index_cpu_FSRCS CPUID_INDEX_7_ECX_1
558#define index_cpu_AMX_FP16 CPUID_INDEX_7_ECX_1
559#define index_cpu_HRESET CPUID_INDEX_7_ECX_1
560#define index_cpu_AVX_IFMA CPUID_INDEX_7_ECX_1
561#define index_cpu_LAM CPUID_INDEX_7_ECX_1
562#define index_cpu_AVX_VNNI_INT8 CPUID_INDEX_7_ECX_1
563#define index_cpu_AVX_NE_CONVERT CPUID_INDEX_7_ECX_1
564#define index_cpu_AMX_COMPLEX CPUID_INDEX_7_ECX_1
565#define index_cpu_PREFETCHI CPUID_INDEX_7_ECX_1
566#define index_cpu_APX_F CPUID_INDEX_7_ECX_1
567
568/* CPUID_INDEX_19. */
569
570/* EBX. */
571#define index_cpu_AESKLE CPUID_INDEX_19
572#define index_cpu_WIDE_KL CPUID_INDEX_19
573
574/* CPUID_INDEX_14_ECX_0. */
575
576/* EBX. */
577#define index_cpu_PTWRITE CPUID_INDEX_14_ECX_0
578
579/* CPUID_INDEX_1. */
580
581/* ECX. */
582#define reg_SSE3 ecx
583#define reg_PCLMULQDQ ecx
584#define reg_DTES64 ecx
585#define reg_MONITOR ecx
586#define reg_DS_CPL ecx
587#define reg_VMX ecx
588#define reg_SMX ecx
589#define reg_EIST ecx
590#define reg_TM2 ecx
591#define reg_SSSE3 ecx
592#define reg_CNXT_ID ecx
593#define reg_SDBG ecx
594#define reg_FMA ecx
595#define reg_CMPXCHG16B ecx
596#define reg_XTPRUPDCTRL ecx
597#define reg_PDCM ecx
598#define reg_INDEX_1_ECX_16 ecx
599#define reg_PCID ecx
600#define reg_DCA ecx
601#define reg_SSE4_1 ecx
602#define reg_SSE4_2 ecx
603#define reg_X2APIC ecx
604#define reg_MOVBE ecx
605#define reg_POPCNT ecx
606#define reg_TSC_DEADLINE ecx
607#define reg_AES ecx
608#define reg_XSAVE ecx
609#define reg_OSXSAVE ecx
610#define reg_AVX ecx
611#define reg_F16C ecx
612#define reg_RDRAND ecx
613#define reg_INDEX_1_ECX_31 ecx
614
615/* EDX. */
616#define reg_FPU edx
617#define reg_VME edx
618#define reg_DE edx
619#define reg_PSE edx
620#define reg_TSC edx
621#define reg_MSR edx
622#define reg_PAE edx
623#define reg_MCE edx
624#define reg_CX8 edx
625#define reg_APIC edx
626#define reg_INDEX_1_EDX_10 edx
627#define reg_SEP edx
628#define reg_MTRR edx
629#define reg_PGE edx
630#define reg_MCA edx
631#define reg_CMOV edx
632#define reg_PAT edx
633#define reg_PSE_36 edx
634#define reg_PSN edx
635#define reg_CLFSH edx
636#define reg_INDEX_1_EDX_20 edx
637#define reg_DS edx
638#define reg_ACPI edx
639#define reg_MMX edx
640#define reg_FXSR edx
641#define reg_SSE edx
642#define reg_SSE2 edx
643#define reg_SS edx
644#define reg_HTT edx
645#define reg_TM edx
646#define reg_INDEX_1_EDX_30 edx
647#define reg_PBE edx
648
649/* CPUID_INDEX_7. */
650
651/* EBX. */
652#define reg_FSGSBASE ebx
653#define reg_TSC_ADJUST ebx
654#define reg_SGX ebx
655#define reg_BMI1 ebx
656#define reg_HLE ebx
657#define reg_BMI2 ebx
658#define reg_AVX2 ebx
659#define reg_INDEX_7_EBX_6 ebx
660#define reg_SMEP ebx
661#define reg_ERMS ebx
662#define reg_INVPCID ebx
663#define reg_RTM ebx
664#define reg_RDT_M ebx
665#define reg_DEPR_FPU_CS_DS ebx
666#define reg_MPX ebx
667#define reg_RDT_A ebx
668#define reg_AVX512F ebx
669#define reg_AVX512DQ ebx
670#define reg_RDSEED ebx
671#define reg_ADX ebx
672#define reg_SMAP ebx
673#define reg_AVX512_IFMA ebx
674#define reg_INDEX_7_EBX_22 ebx
675#define reg_CLFLUSHOPT ebx
676#define reg_CLWB ebx
677#define reg_TRACE ebx
678#define reg_AVX512PF ebx
679#define reg_AVX512ER ebx
680#define reg_AVX512CD ebx
681#define reg_SHA ebx
682#define reg_AVX512BW ebx
683#define reg_AVX512VL ebx
684
685/* ECX. */
686#define reg_PREFETCHWT1 ecx
687#define reg_AVX512_VBMI ecx
688#define reg_UMIP ecx
689#define reg_PKU ecx
690#define reg_OSPKE ecx
691#define reg_WAITPKG ecx
692#define reg_AVX512_VBMI2 ecx
693#define reg_SHSTK ecx
694#define reg_GFNI ecx
695#define reg_VAES ecx
696#define reg_VPCLMULQDQ ecx
697#define reg_AVX512_VNNI ecx
698#define reg_AVX512_BITALG ecx
699#define reg_INDEX_7_ECX_13 ecx
700#define reg_AVX512_VPOPCNTDQ ecx
701#define reg_INDEX_7_ECX_15 ecx
702#define reg_INDEX_7_ECX_16 ecx
703#define reg_RDPID ecx
704#define reg_KL ecx
705#define reg_INDEX_7_ECX_24 ecx
706#define reg_CLDEMOTE ecx
707#define reg_INDEX_7_ECX_26 ecx
708#define reg_MOVDIRI ecx
709#define reg_MOVDIR64B ecx
710#define reg_ENQCMD ecx
711#define reg_SGX_LC ecx
712#define reg_PKS ecx
713
714/* EDX. */
715#define reg_INDEX_7_EDX_0 edx
716#define reg_INDEX_7_EDX_1 edx
717#define reg_AVX512_4VNNIW edx
718#define reg_AVX512_4FMAPS edx
719#define reg_FSRM edx
720#define reg_UINTR edx
721#define reg_INDEX_7_EDX_6 edx
722#define reg_INDEX_7_EDX_7 edx
723#define reg_AVX512_VP2INTERSECT edx
724#define reg_INDEX_7_EDX_9 edx
725#define reg_MD_CLEAR edx
726#define reg_RTM_ALWAYS_ABORT edx
727#define reg_INDEX_7_EDX_12 edx
728#define reg_INDEX_7_EDX_13 edx
729#define reg_SERIALIZE edx
730#define reg_HYBRID edx
731#define reg_TSXLDTRK edx
732#define reg_INDEX_7_EDX_17 edx
733#define reg_PCONFIG edx
734#define reg_INDEX_7_EDX_19 edx
735#define reg_IBT edx
736#define reg_INDEX_7_EDX_21 edx
737#define reg_AMX_BF16 edx
738#define reg_AVX512_FP16 edx
739#define reg_AMX_TILE edx
740#define reg_AMX_INT8 edx
741#define reg_IBRS_IBPB edx
742#define reg_STIBP edx
743#define reg_L1D_FLUSH edx
744#define reg_ARCH_CAPABILITIES edx
745#define reg_CORE_CAPABILITIES edx
746#define reg_SSBD edx
747
748/* CPUID_INDEX_80000001. */
749
750/* ECX. */
751#define reg_LAHF64_SAHF64 ecx
752#define reg_SVM ecx
753#define reg_LZCNT ecx
754#define reg_SSE4A ecx
755#define reg_PREFETCHW ecx
756#define reg_XOP ecx
757#define reg_LWP ecx
758#define reg_FMA4 ecx
759#define reg_TBM ecx
760
761/* EDX. */
762#define reg_SYSCALL_SYSRET edx
763#define reg_NX edx
764#define reg_PAGE1GB edx
765#define reg_RDTSCP edx
766#define reg_LM edx
767
768/* CPUID_INDEX_D_ECX_1. */
769
770/* EAX. */
771#define reg_XSAVEOPT eax
772#define reg_XSAVEC eax
773#define reg_XGETBV_ECX_1 eax
774#define reg_XSAVES eax
775#define reg_XFD eax
776
777/* CPUID_INDEX_80000007. */
778
779/* EDX. */
780#define reg_INVARIANT_TSC edx
781
782/* CPUID_INDEX_80000008. */
783
784/* EBX. */
785#define reg_WBNOINVD ebx
786#define reg_AMD_IBPB ebx
787#define reg_AMD_IBRS ebx
788#define reg_AMD_STIBP ebx
789#define reg_AMD_SSBD ebx
790#define reg_AMD_VIRT_SSBD ebx
791
792/* CPUID_INDEX_7_ECX_1. */
793
794/* EAX. */
795#define reg_RAO_INT eax
796#define reg_AVX_VNNI eax
797#define reg_AVX512_BF16 eax
798#define reg_CMPCCXADD eax
799#define reg_FZLRM eax
800#define reg_FSRS eax
801#define reg_FSRCS eax
802#define reg_AMX_FP16 eax
803#define reg_HRESET eax
804#define reg_AVX_IFMA eax
805#define reg_LAM eax
806
807/* EDX. */
808#define reg_AVX_VNNI_INT8 edx
809#define reg_AVX_NE_CONVERT edx
810#define reg_AMX_COMPLEX edx
811#define reg_PREFETCHI edx
812#define reg_APX_F edx
813
814/* CPUID_INDEX_19. */
815
816/* EBX. */
817#define reg_AESKLE ebx
818#define reg_WIDE_KL ebx
819
820/* CPUID_INDEX_14_ECX_0. */
821
822/* EBX. */
823#define reg_PTWRITE ebx
824
825/* PREFERRED_FEATURE_INDEX_1. First define the bitindex values
826 sequentially, then define the bit_arch* and index_arch_* lookup
827 constants. */
828enum
829 {
830#define BIT(x) _bitindex_arch_##x ,
831#include "cpu-features-preferred_feature_index_1.def"
832#undef BIT
833 };
834enum
835 {
836#define BIT(x) \
837 bit_arch_##x = 1u << _bitindex_arch_##x , \
838 index_arch_##x = PREFERRED_FEATURE_INDEX_1,
839#include "cpu-features-preferred_feature_index_1.def"
840#undef BIT
841 };
842
843/* XCR0 Feature flags. */
844#define bit_XMM_state (1u << 1)
845#define bit_YMM_state (1u << 2)
846#define bit_Opmask_state (1u << 5)
847#define bit_ZMM0_15_state (1u << 6)
848#define bit_ZMM16_31_state (1u << 7)
849#define bit_XTILECFG_state (1u << 17)
850#define bit_XTILEDATA_state (1u << 18)
851#define bit_APX_state (1u << 19)
852
853enum cpu_features_kind
854{
855 arch_kind_unknown = 0,
856 arch_kind_intel,
857 arch_kind_amd,
858 arch_kind_zhaoxin,
859 arch_kind_other
860};
861
862struct cpu_features_basic
863{
864 enum cpu_features_kind kind;
865 int max_cpuid;
866 unsigned int family;
867 unsigned int model;
868 unsigned int stepping;
869};
870
871struct cpuid_registers
872{
873 unsigned int eax;
874 unsigned int ebx;
875 unsigned int ecx;
876 unsigned int edx;
877};
878
879struct cpuid_feature_internal
880{
881 union
882 {
883 unsigned int cpuid_array[4];
884 struct cpuid_registers cpuid;
885 };
886 union
887 {
888 unsigned int active_array[4];
889 struct cpuid_registers active;
890 };
891};
892
893/* NB: When adding new fields, update sysdeps/x86/dl-diagnostics-cpu.c
894 to print them. */
895struct cpu_features
896{
897 struct cpu_features_basic basic;
898 struct cpuid_feature_internal features[CPUID_INDEX_MAX];
899 unsigned int preferred[PREFERRED_FEATURE_INDEX_MAX];
900 /* X86 micro-architecture ISA levels. */
901 unsigned int isa_1;
902 /* The state size for XSAVEC or XSAVE. The type must be unsigned long
903 int so that we use
904
905 sub xsave_state_size_offset(%rip) %RSP_LP
906
907 in _dl_runtime_resolve. */
908 unsigned long int xsave_state_size;
909 /* The full state size for XSAVE when XSAVEC is disabled by
910
911 GLIBC_TUNABLES=glibc.cpu.hwcaps=-XSAVEC
912 */
913 unsigned int xsave_state_full_size;
914 /* Data cache size for use in memory and string routines, typically
915 L1 size. */
916 unsigned long int data_cache_size;
917 /* Shared cache size for use in memory and string routines, typically
918 L2 or L3 size. */
919 unsigned long int shared_cache_size;
920 /* Threshold to use non temporal store. */
921 unsigned long int non_temporal_threshold;
922 /* Threshold to use "rep movsb". */
923 unsigned long int rep_movsb_threshold;
924 /* Threshold to stop using "rep movsb". */
925 unsigned long int rep_movsb_stop_threshold;
926 /* Threshold to use "rep stosb". */
927 unsigned long int rep_stosb_threshold;
928 /* _SC_LEVEL1_ICACHE_SIZE. */
929 unsigned long int level1_icache_size;
930 /* _SC_LEVEL1_ICACHE_LINESIZE. */
931 unsigned long int level1_icache_linesize;
932 /* _SC_LEVEL1_DCACHE_SIZE. */
933 unsigned long int level1_dcache_size;
934 /* _SC_LEVEL1_DCACHE_ASSOC. */
935 unsigned long int level1_dcache_assoc;
936 /* _SC_LEVEL1_DCACHE_LINESIZE. */
937 unsigned long int level1_dcache_linesize;
938 /* _SC_LEVEL2_CACHE_ASSOC. */
939 unsigned long int level2_cache_size;
940 /* _SC_LEVEL2_DCACHE_ASSOC. */
941 unsigned long int level2_cache_assoc;
942 /* _SC_LEVEL2_CACHE_LINESIZE. */
943 unsigned long int level2_cache_linesize;
944 /* /_SC_LEVEL3_CACHE_SIZE. */
945 unsigned long int level3_cache_size;
946 /* _SC_LEVEL3_CACHE_ASSOC. */
947 unsigned long int level3_cache_assoc;
948 /* _SC_LEVEL3_CACHE_LINESIZE. */
949 unsigned long int level3_cache_linesize;
950 /* /_SC_LEVEL4_CACHE_SIZE. */
951 unsigned long int level4_cache_size;
952 /* When no user non_temporal_threshold is specified. We default to
953 cachesize / cachesize_non_temporal_divisor. */
954 unsigned long int cachesize_non_temporal_divisor;
955};
956
957/* Get a pointer to the CPU features structure. */
958extern const struct cpu_features *_dl_x86_get_cpu_features (void)
959 __attribute__ ((pure));
960
961#define __get_cpu_features() _dl_x86_get_cpu_features()
962
963#if defined (_LIBC) && !IS_IN (nonlib)
964/* Unused for x86. */
965# define INIT_ARCH()
966# define _dl_x86_get_cpu_features() (&GLRO(dl_x86_cpu_features))
967extern void _dl_x86_init_cpu_features (void) attribute_hidden;
968#endif
969
970#ifdef __x86_64__
971# define HAS_CPUID 1
972#elif (defined __i586__ || defined __pentium__ \
973 || defined __geode__ || defined __k6__)
974# define HAS_CPUID 1
975# define HAS_I586 1
976# define HAS_I686 HAS_ARCH_FEATURE (I686)
977#elif defined __i486__
978# define HAS_CPUID 0
979# define HAS_I586 HAS_ARCH_FEATURE (I586)
980# define HAS_I686 HAS_ARCH_FEATURE (I686)
981#else
982# define HAS_CPUID 1
983# define HAS_I586 1
984# define HAS_I686 1
985#endif
986
987#endif /* include/cpu-features.h */
988