1/* Data structure for x86 CPU features.
2 Copyright (C) 2020-2021 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <https://www.gnu.org/licenses/>. */
18
19#ifndef _PRIVATE_CPU_FEATURES_H
20#define _PRIVATE_CPU_FEATURES_H 1
21
22#ifdef _CPU_FEATURES_H
23# error this should be impossible
24#endif
25
26/* Get data structures without inline functions. */
27#define _SYS_PLATFORM_X86_H
28#include <bits/platform/x86.h>
29
30enum
31{
32 CPUID_INDEX_MAX = CPUID_INDEX_19 + 1
33};
34
35enum
36{
37 /* The integer bit array index for the first set of preferred feature
38 bits. */
39 PREFERRED_FEATURE_INDEX_1 = 0,
40 /* The current maximum size of the feature integer bit array. */
41 PREFERRED_FEATURE_INDEX_MAX
42};
43
44/* Only used directly in cpu-features.c. */
45#define CPU_FEATURE_SET(ptr, name) \
46 ptr->features[index_cpu_##name].usable.reg_##name |= bit_cpu_##name;
47#define CPU_FEATURE_UNSET(ptr, name) \
48 ptr->features[index_cpu_##name].usable.reg_##name &= ~bit_cpu_##name;
49#define CPU_FEATURE_SET_USABLE(ptr, name) \
50 ptr->features[index_cpu_##name].usable.reg_##name \
51 |= ptr->features[index_cpu_##name].cpuid.reg_##name & bit_cpu_##name;
52#define CPU_FEATURE_PREFERRED_P(ptr, name) \
53 ((ptr->preferred[index_arch_##name] & bit_arch_##name) != 0)
54
55#define CPU_FEATURE_CHECK_P(ptr, name, check) \
56 ((ptr->features[index_cpu_##name].check.reg_##name \
57 & bit_cpu_##name) != 0)
58#define CPU_FEATURE_CPU_P(ptr, name) \
59 CPU_FEATURE_CHECK_P (ptr, name, cpuid)
60#define CPU_FEATURE_USABLE_P(ptr, name) \
61 CPU_FEATURE_CHECK_P (ptr, name, usable)
62
63/* HAS_CPU_FEATURE evaluates to true if CPU supports the feature. */
64#define HAS_CPU_FEATURE(name) \
65 CPU_FEATURE_CPU_P (__get_cpu_features (), name)
66/* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */
67#define CPU_FEATURE_USABLE(name) \
68 CPU_FEATURE_USABLE_P (__get_cpu_features (), name)
69/* CPU_FEATURE_PREFER evaluates to true if we prefer the feature at
70 runtime. */
71#define CPU_FEATURE_PREFERRED(name) \
72 CPU_FEATURE_PREFERRED_P(__get_cpu_features (), name)
73
74#define CPU_FEATURES_CPU_P(ptr, name) \
75 CPU_FEATURE_CPU_P (ptr, name)
76#define CPU_FEATURES_ARCH_P(ptr, name) \
77 CPU_FEATURE_PREFERRED_P (ptr, name)
78#define HAS_ARCH_FEATURE(name) \
79 CPU_FEATURE_PREFERRED (name)
80
81/* CPU features. */
82
83/* CPUID_INDEX_1. */
84
85/* ECX. */
86#define bit_cpu_SSE3 (1u << 0)
87#define bit_cpu_PCLMULQDQ (1u << 1)
88#define bit_cpu_DTES64 (1u << 2)
89#define bit_cpu_MONITOR (1u << 3)
90#define bit_cpu_DS_CPL (1u << 4)
91#define bit_cpu_VMX (1u << 5)
92#define bit_cpu_SMX (1u << 6)
93#define bit_cpu_EIST (1u << 7)
94#define bit_cpu_TM2 (1u << 8)
95#define bit_cpu_SSSE3 (1u << 9)
96#define bit_cpu_CNXT_ID (1u << 10)
97#define bit_cpu_SDBG (1u << 11)
98#define bit_cpu_FMA (1u << 12)
99#define bit_cpu_CMPXCHG16B (1u << 13)
100#define bit_cpu_XTPRUPDCTRL (1u << 14)
101#define bit_cpu_PDCM (1u << 15)
102#define bit_cpu_INDEX_1_ECX_16 (1u << 16)
103#define bit_cpu_PCID (1u << 17)
104#define bit_cpu_DCA (1u << 18)
105#define bit_cpu_SSE4_1 (1u << 19)
106#define bit_cpu_SSE4_2 (1u << 20)
107#define bit_cpu_X2APIC (1u << 21)
108#define bit_cpu_MOVBE (1u << 22)
109#define bit_cpu_POPCNT (1u << 23)
110#define bit_cpu_TSC_DEADLINE (1u << 24)
111#define bit_cpu_AES (1u << 25)
112#define bit_cpu_XSAVE (1u << 26)
113#define bit_cpu_OSXSAVE (1u << 27)
114#define bit_cpu_AVX (1u << 28)
115#define bit_cpu_F16C (1u << 29)
116#define bit_cpu_RDRAND (1u << 30)
117#define bit_cpu_INDEX_1_ECX_31 (1u << 31)
118
119/* EDX. */
120#define bit_cpu_FPU (1u << 0)
121#define bit_cpu_VME (1u << 1)
122#define bit_cpu_DE (1u << 2)
123#define bit_cpu_PSE (1u << 3)
124#define bit_cpu_TSC (1u << 4)
125#define bit_cpu_MSR (1u << 5)
126#define bit_cpu_PAE (1u << 6)
127#define bit_cpu_MCE (1u << 7)
128#define bit_cpu_CX8 (1u << 8)
129#define bit_cpu_APIC (1u << 9)
130#define bit_cpu_INDEX_1_EDX_10 (1u << 10)
131#define bit_cpu_SEP (1u << 11)
132#define bit_cpu_MTRR (1u << 12)
133#define bit_cpu_PGE (1u << 13)
134#define bit_cpu_MCA (1u << 14)
135#define bit_cpu_CMOV (1u << 15)
136#define bit_cpu_PAT (1u << 16)
137#define bit_cpu_PSE_36 (1u << 17)
138#define bit_cpu_PSN (1u << 18)
139#define bit_cpu_CLFSH (1u << 19)
140#define bit_cpu_INDEX_1_EDX_20 (1u << 20)
141#define bit_cpu_DS (1u << 21)
142#define bit_cpu_ACPI (1u << 22)
143#define bit_cpu_MMX (1u << 23)
144#define bit_cpu_FXSR (1u << 24)
145#define bit_cpu_SSE (1u << 25)
146#define bit_cpu_SSE2 (1u << 26)
147#define bit_cpu_SS (1u << 27)
148#define bit_cpu_HTT (1u << 28)
149#define bit_cpu_TM (1u << 29)
150#define bit_cpu_INDEX_1_EDX_30 (1u << 30)
151#define bit_cpu_PBE (1u << 31)
152
153/* CPUID_INDEX_7. */
154
155/* EBX. */
156#define bit_cpu_FSGSBASE (1u << 0)
157#define bit_cpu_TSC_ADJUST (1u << 1)
158#define bit_cpu_SGX (1u << 2)
159#define bit_cpu_BMI1 (1u << 3)
160#define bit_cpu_HLE (1u << 4)
161#define bit_cpu_AVX2 (1u << 5)
162#define bit_cpu_INDEX_7_EBX_6 (1u << 6)
163#define bit_cpu_SMEP (1u << 7)
164#define bit_cpu_BMI2 (1u << 8)
165#define bit_cpu_ERMS (1u << 9)
166#define bit_cpu_INVPCID (1u << 10)
167#define bit_cpu_RTM (1u << 11)
168#define bit_cpu_RDT_M (1u << 12)
169#define bit_cpu_DEPR_FPU_CS_DS (1u << 13)
170#define bit_cpu_MPX (1u << 14)
171#define bit_cpu_RDT_A (1u << 15)
172#define bit_cpu_AVX512F (1u << 16)
173#define bit_cpu_AVX512DQ (1u << 17)
174#define bit_cpu_RDSEED (1u << 18)
175#define bit_cpu_ADX (1u << 19)
176#define bit_cpu_SMAP (1u << 20)
177#define bit_cpu_AVX512_IFMA (1u << 21)
178#define bit_cpu_INDEX_7_EBX_22 (1u << 22)
179#define bit_cpu_CLFLUSHOPT (1u << 23)
180#define bit_cpu_CLWB (1u << 24)
181#define bit_cpu_TRACE (1u << 25)
182#define bit_cpu_AVX512PF (1u << 26)
183#define bit_cpu_AVX512ER (1u << 27)
184#define bit_cpu_AVX512CD (1u << 28)
185#define bit_cpu_SHA (1u << 29)
186#define bit_cpu_AVX512BW (1u << 30)
187#define bit_cpu_AVX512VL (1u << 31)
188
189/* ECX. */
190#define bit_cpu_PREFETCHWT1 (1u << 0)
191#define bit_cpu_AVX512_VBMI (1u << 1)
192#define bit_cpu_UMIP (1u << 2)
193#define bit_cpu_PKU (1u << 3)
194#define bit_cpu_OSPKE (1u << 4)
195#define bit_cpu_WAITPKG (1u << 5)
196#define bit_cpu_AVX512_VBMI2 (1u << 6)
197#define bit_cpu_SHSTK (1u << 7)
198#define bit_cpu_GFNI (1u << 8)
199#define bit_cpu_VAES (1u << 9)
200#define bit_cpu_VPCLMULQDQ (1u << 10)
201#define bit_cpu_AVX512_VNNI (1u << 11)
202#define bit_cpu_AVX512_BITALG (1u << 12)
203#define bit_cpu_INDEX_7_ECX_13 (1u << 13)
204#define bit_cpu_AVX512_VPOPCNTDQ (1u << 14)
205#define bit_cpu_INDEX_7_ECX_15 (1u << 15)
206#define bit_cpu_INDEX_7_ECX_16 (1u << 16)
207/* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX
208 instructions in 64-bit mode. */
209#define bit_cpu_RDPID (1u << 22)
210#define bit_cpu_KL (1u << 23)
211#define bit_cpu_INDEX_7_ECX_24 (1u << 24)
212#define bit_cpu_CLDEMOTE (1u << 25)
213#define bit_cpu_INDEX_7_ECX_26 (1u << 26)
214#define bit_cpu_MOVDIRI (1u << 27)
215#define bit_cpu_MOVDIR64B (1u << 28)
216#define bit_cpu_ENQCMD (1u << 29)
217#define bit_cpu_SGX_LC (1u << 30)
218#define bit_cpu_PKS (1u << 31)
219
220/* EDX. */
221#define bit_cpu_INDEX_7_EDX_0 (1u << 0)
222#define bit_cpu_INDEX_7_EDX_1 (1u << 1)
223#define bit_cpu_AVX512_4VNNIW (1u << 2)
224#define bit_cpu_AVX512_4FMAPS (1u << 3)
225#define bit_cpu_FSRM (1u << 4)
226#define bit_cpu_UINTR (1u << 5)
227#define bit_cpu_INDEX_7_EDX_6 (1u << 6)
228#define bit_cpu_INDEX_7_EDX_7 (1u << 7)
229#define bit_cpu_AVX512_VP2INTERSECT (1u << 8)
230#define bit_cpu_INDEX_7_EDX_9 (1u << 9)
231#define bit_cpu_MD_CLEAR (1u << 10)
232#define bit_cpu_INDEX_7_EDX_11 (1u << 11)
233#define bit_cpu_INDEX_7_EDX_12 (1u << 12)
234#define bit_cpu_INDEX_7_EDX_13 (1u << 13)
235#define bit_cpu_SERIALIZE (1u << 14)
236#define bit_cpu_HYBRID (1u << 15)
237#define bit_cpu_TSXLDTRK (1u << 16)
238#define bit_cpu_INDEX_7_EDX_17 (1u << 17)
239#define bit_cpu_PCONFIG (1u << 18)
240#define bit_cpu_INDEX_7_EDX_19 (1u << 19)
241#define bit_cpu_IBT (1u << 20)
242#define bit_cpu_INDEX_7_EDX_21 (1u << 21)
243#define bit_cpu_AMX_BF16 (1u << 22)
244#define bit_cpu_AVX512_FP16 (1u << 23)
245#define bit_cpu_AMX_TILE (1u << 24)
246#define bit_cpu_AMX_INT8 (1u << 25)
247#define bit_cpu_IBRS_IBPB (1u << 26)
248#define bit_cpu_STIBP (1u << 27)
249#define bit_cpu_L1D_FLUSH (1u << 28)
250#define bit_cpu_ARCH_CAPABILITIES (1u << 29)
251#define bit_cpu_CORE_CAPABILITIES (1u << 30)
252#define bit_cpu_SSBD (1u << 31)
253
254/* CPUID_INDEX_80000001. */
255
256/* ECX. */
257#define bit_cpu_LAHF64_SAHF64 (1u << 0)
258#define bit_cpu_SVM (1u << 2)
259#define bit_cpu_LZCNT (1u << 5)
260#define bit_cpu_SSE4A (1u << 6)
261#define bit_cpu_PREFETCHW (1u << 8)
262#define bit_cpu_XOP (1u << 11)
263#define bit_cpu_LWP (1u << 15)
264#define bit_cpu_FMA4 (1u << 16)
265#define bit_cpu_TBM (1u << 21)
266
267/* EDX. */
268#define bit_cpu_SYSCALL_SYSRET (1u << 11)
269#define bit_cpu_NX (1u << 20)
270#define bit_cpu_PAGE1GB (1u << 26)
271#define bit_cpu_RDTSCP (1u << 27)
272#define bit_cpu_LM (1u << 29)
273
274/* CPUID_INDEX_D_ECX_1. */
275
276/* EAX. */
277#define bit_cpu_XSAVEOPT (1u << 0)
278#define bit_cpu_XSAVEC (1u << 1)
279#define bit_cpu_XGETBV_ECX_1 (1u << 2)
280#define bit_cpu_XSAVES (1u << 3)
281#define bit_cpu_XFD (1u << 4)
282
283/* CPUID_INDEX_80000007. */
284
285/* EDX. */
286#define bit_cpu_INVARIANT_TSC (1u << 8)
287
288/* CPUID_INDEX_80000008. */
289
290/* EBX. */
291#define bit_cpu_WBNOINVD (1u << 9)
292
293/* CPUID_INDEX_7_ECX_1. */
294
295/* EAX. */
296#define bit_cpu_AVX_VNNI (1u << 4)
297#define bit_cpu_AVX512_BF16 (1u << 5)
298#define bit_cpu_FZLRM (1u << 10)
299#define bit_cpu_FSRS (1u << 11)
300#define bit_cpu_FSRCS (1u << 12)
301#define bit_cpu_HRESET (1u << 22)
302#define bit_cpu_LAM (1u << 26)
303
304/* CPUID_INDEX_19. */
305
306/* EBX. */
307#define bit_cpu_AESKLE (1u << 0)
308#define bit_cpu_WIDE_KL (1u << 2)
309
310/* CPUID_INDEX_1. */
311
312/* ECX. */
313#define index_cpu_SSE3 CPUID_INDEX_1
314#define index_cpu_PCLMULQDQ CPUID_INDEX_1
315#define index_cpu_DTES64 CPUID_INDEX_1
316#define index_cpu_MONITOR CPUID_INDEX_1
317#define index_cpu_DS_CPL CPUID_INDEX_1
318#define index_cpu_VMX CPUID_INDEX_1
319#define index_cpu_SMX CPUID_INDEX_1
320#define index_cpu_EIST CPUID_INDEX_1
321#define index_cpu_TM2 CPUID_INDEX_1
322#define index_cpu_SSSE3 CPUID_INDEX_1
323#define index_cpu_CNXT_ID CPUID_INDEX_1
324#define index_cpu_SDBG CPUID_INDEX_1
325#define index_cpu_FMA CPUID_INDEX_1
326#define index_cpu_CMPXCHG16B CPUID_INDEX_1
327#define index_cpu_XTPRUPDCTRL CPUID_INDEX_1
328#define index_cpu_PDCM CPUID_INDEX_1
329#define index_cpu_INDEX_1_ECX_16 CPUID_INDEX_1
330#define index_cpu_PCID CPUID_INDEX_1
331#define index_cpu_DCA CPUID_INDEX_1
332#define index_cpu_SSE4_1 CPUID_INDEX_1
333#define index_cpu_SSE4_2 CPUID_INDEX_1
334#define index_cpu_X2APIC CPUID_INDEX_1
335#define index_cpu_MOVBE CPUID_INDEX_1
336#define index_cpu_POPCNT CPUID_INDEX_1
337#define index_cpu_TSC_DEADLINE CPUID_INDEX_1
338#define index_cpu_AES CPUID_INDEX_1
339#define index_cpu_XSAVE CPUID_INDEX_1
340#define index_cpu_OSXSAVE CPUID_INDEX_1
341#define index_cpu_AVX CPUID_INDEX_1
342#define index_cpu_F16C CPUID_INDEX_1
343#define index_cpu_RDRAND CPUID_INDEX_1
344#define index_cpu_INDEX_1_ECX_31 CPUID_INDEX_1
345
346/* ECX. */
347#define index_cpu_FPU CPUID_INDEX_1
348#define index_cpu_VME CPUID_INDEX_1
349#define index_cpu_DE CPUID_INDEX_1
350#define index_cpu_PSE CPUID_INDEX_1
351#define index_cpu_TSC CPUID_INDEX_1
352#define index_cpu_MSR CPUID_INDEX_1
353#define index_cpu_PAE CPUID_INDEX_1
354#define index_cpu_MCE CPUID_INDEX_1
355#define index_cpu_CX8 CPUID_INDEX_1
356#define index_cpu_APIC CPUID_INDEX_1
357#define index_cpu_INDEX_1_EDX_10 CPUID_INDEX_1
358#define index_cpu_SEP CPUID_INDEX_1
359#define index_cpu_MTRR CPUID_INDEX_1
360#define index_cpu_PGE CPUID_INDEX_1
361#define index_cpu_MCA CPUID_INDEX_1
362#define index_cpu_CMOV CPUID_INDEX_1
363#define index_cpu_PAT CPUID_INDEX_1
364#define index_cpu_PSE_36 CPUID_INDEX_1
365#define index_cpu_PSN CPUID_INDEX_1
366#define index_cpu_CLFSH CPUID_INDEX_1
367#define index_cpu_INDEX_1_EDX_20 CPUID_INDEX_1
368#define index_cpu_DS CPUID_INDEX_1
369#define index_cpu_ACPI CPUID_INDEX_1
370#define index_cpu_MMX CPUID_INDEX_1
371#define index_cpu_FXSR CPUID_INDEX_1
372#define index_cpu_SSE CPUID_INDEX_1
373#define index_cpu_SSE2 CPUID_INDEX_1
374#define index_cpu_SS CPUID_INDEX_1
375#define index_cpu_HTT CPUID_INDEX_1
376#define index_cpu_TM CPUID_INDEX_1
377#define index_cpu_INDEX_1_EDX_30 CPUID_INDEX_1
378#define index_cpu_PBE CPUID_INDEX_1
379
380/* CPUID_INDEX_7. */
381
382/* EBX. */
383#define index_cpu_FSGSBASE CPUID_INDEX_7
384#define index_cpu_TSC_ADJUST CPUID_INDEX_7
385#define index_cpu_SGX CPUID_INDEX_7
386#define index_cpu_BMI1 CPUID_INDEX_7
387#define index_cpu_HLE CPUID_INDEX_7
388#define index_cpu_AVX2 CPUID_INDEX_7
389#define index_cpu_INDEX_7_EBX_6 CPUID_INDEX_7
390#define index_cpu_SMEP CPUID_INDEX_7
391#define index_cpu_BMI2 CPUID_INDEX_7
392#define index_cpu_ERMS CPUID_INDEX_7
393#define index_cpu_INVPCID CPUID_INDEX_7
394#define index_cpu_RTM CPUID_INDEX_7
395#define index_cpu_RDT_M CPUID_INDEX_7
396#define index_cpu_DEPR_FPU_CS_DS CPUID_INDEX_7
397#define index_cpu_MPX CPUID_INDEX_7
398#define index_cpu_RDT_A CPUID_INDEX_7
399#define index_cpu_AVX512F CPUID_INDEX_7
400#define index_cpu_AVX512DQ CPUID_INDEX_7
401#define index_cpu_RDSEED CPUID_INDEX_7
402#define index_cpu_ADX CPUID_INDEX_7
403#define index_cpu_SMAP CPUID_INDEX_7
404#define index_cpu_AVX512_IFMA CPUID_INDEX_7
405#define index_cpu_INDEX_7_EBX_22 CPUID_INDEX_7
406#define index_cpu_CLFLUSHOPT CPUID_INDEX_7
407#define index_cpu_CLWB CPUID_INDEX_7
408#define index_cpu_TRACE CPUID_INDEX_7
409#define index_cpu_AVX512PF CPUID_INDEX_7
410#define index_cpu_AVX512ER CPUID_INDEX_7
411#define index_cpu_AVX512CD CPUID_INDEX_7
412#define index_cpu_SHA CPUID_INDEX_7
413#define index_cpu_AVX512BW CPUID_INDEX_7
414#define index_cpu_AVX512VL CPUID_INDEX_7
415
416/* ECX. */
417#define index_cpu_PREFETCHWT1 CPUID_INDEX_7
418#define index_cpu_AVX512_VBMI CPUID_INDEX_7
419#define index_cpu_UMIP CPUID_INDEX_7
420#define index_cpu_PKU CPUID_INDEX_7
421#define index_cpu_OSPKE CPUID_INDEX_7
422#define index_cpu_WAITPKG CPUID_INDEX_7
423#define index_cpu_AVX512_VBMI2 CPUID_INDEX_7
424#define index_cpu_SHSTK CPUID_INDEX_7
425#define index_cpu_GFNI CPUID_INDEX_7
426#define index_cpu_VAES CPUID_INDEX_7
427#define index_cpu_VPCLMULQDQ CPUID_INDEX_7
428#define index_cpu_AVX512_VNNI CPUID_INDEX_7
429#define index_cpu_AVX512_BITALG CPUID_INDEX_7
430#define index_cpu_INDEX_7_ECX_13 CPUID_INDEX_7
431#define index_cpu_AVX512_VPOPCNTDQ CPUID_INDEX_7
432#define index_cpu_INDEX_7_ECX_15 CPUID_INDEX_7
433#define index_cpu_INDEX_7_ECX_16 CPUID_INDEX_7
434#define index_cpu_RDPID CPUID_INDEX_7
435#define index_cpu_KL CPUID_INDEX_7
436#define index_cpu_INDEX_7_ECX_24 CPUID_INDEX_7
437#define index_cpu_CLDEMOTE CPUID_INDEX_7
438#define index_cpu_INDEX_7_ECX_26 CPUID_INDEX_7
439#define index_cpu_MOVDIRI CPUID_INDEX_7
440#define index_cpu_MOVDIR64B CPUID_INDEX_7
441#define index_cpu_ENQCMD CPUID_INDEX_7
442#define index_cpu_SGX_LC CPUID_INDEX_7
443#define index_cpu_PKS CPUID_INDEX_7
444
445/* EDX. */
446#define index_cpu_INDEX_7_EDX_0 CPUID_INDEX_7
447#define index_cpu_INDEX_7_EDX_1 CPUID_INDEX_7
448#define index_cpu_AVX512_4VNNIW CPUID_INDEX_7
449#define index_cpu_AVX512_4FMAPS CPUID_INDEX_7
450#define index_cpu_FSRM CPUID_INDEX_7
451#define index_cpu_UINTR CPUID_INDEX_7
452#define index_cpu_INDEX_7_EDX_6 CPUID_INDEX_7
453#define index_cpu_INDEX_7_EDX_7 CPUID_INDEX_7
454#define index_cpu_AVX512_VP2INTERSECT CPUID_INDEX_7
455#define index_cpu_INDEX_7_EDX_9 CPUID_INDEX_7
456#define index_cpu_MD_CLEAR CPUID_INDEX_7
457#define index_cpu_INDEX_7_EDX_11 CPUID_INDEX_7
458#define index_cpu_INDEX_7_EDX_12 CPUID_INDEX_7
459#define index_cpu_INDEX_7_EDX_13 CPUID_INDEX_7
460#define index_cpu_SERIALIZE CPUID_INDEX_7
461#define index_cpu_HYBRID CPUID_INDEX_7
462#define index_cpu_TSXLDTRK CPUID_INDEX_7
463#define index_cpu_INDEX_7_EDX_17 CPUID_INDEX_7
464#define index_cpu_PCONFIG CPUID_INDEX_7
465#define index_cpu_INDEX_7_EDX_19 CPUID_INDEX_7
466#define index_cpu_IBT CPUID_INDEX_7
467#define index_cpu_INDEX_7_EDX_21 CPUID_INDEX_7
468#define index_cpu_AMX_BF16 CPUID_INDEX_7
469#define index_cpu_AVX512_FP16 CPUID_INDEX_7
470#define index_cpu_AMX_TILE CPUID_INDEX_7
471#define index_cpu_AMX_INT8 CPUID_INDEX_7
472#define index_cpu_IBRS_IBPB CPUID_INDEX_7
473#define index_cpu_STIBP CPUID_INDEX_7
474#define index_cpu_L1D_FLUSH CPUID_INDEX_7
475#define index_cpu_ARCH_CAPABILITIES CPUID_INDEX_7
476#define index_cpu_CORE_CAPABILITIES CPUID_INDEX_7
477#define index_cpu_SSBD CPUID_INDEX_7
478
479/* CPUID_INDEX_80000001. */
480
481/* ECX. */
482#define index_cpu_LAHF64_SAHF64 CPUID_INDEX_80000001
483#define index_cpu_SVM CPUID_INDEX_80000001
484#define index_cpu_LZCNT CPUID_INDEX_80000001
485#define index_cpu_SSE4A CPUID_INDEX_80000001
486#define index_cpu_PREFETCHW CPUID_INDEX_80000001
487#define index_cpu_XOP CPUID_INDEX_80000001
488#define index_cpu_LWP CPUID_INDEX_80000001
489#define index_cpu_FMA4 CPUID_INDEX_80000001
490#define index_cpu_TBM CPUID_INDEX_80000001
491
492/* EDX. */
493#define index_cpu_SYSCALL_SYSRET CPUID_INDEX_80000001
494#define index_cpu_NX CPUID_INDEX_80000001
495#define index_cpu_PAGE1GB CPUID_INDEX_80000001
496#define index_cpu_RDTSCP CPUID_INDEX_80000001
497#define index_cpu_LM CPUID_INDEX_80000001
498
499/* CPUID_INDEX_D_ECX_1. */
500
501/* EAX. */
502#define index_cpu_XSAVEOPT CPUID_INDEX_D_ECX_1
503#define index_cpu_XSAVEC CPUID_INDEX_D_ECX_1
504#define index_cpu_XGETBV_ECX_1 CPUID_INDEX_D_ECX_1
505#define index_cpu_XSAVES CPUID_INDEX_D_ECX_1
506#define index_cpu_XFD CPUID_INDEX_D_ECX_1
507
508/* CPUID_INDEX_80000007. */
509
510/* EDX. */
511#define index_cpu_INVARIANT_TSC CPUID_INDEX_80000007
512
513/* CPUID_INDEX_80000008. */
514
515/* EBX. */
516#define index_cpu_WBNOINVD CPUID_INDEX_80000008
517
518/* CPUID_INDEX_7_ECX_1. */
519
520/* EAX. */
521#define index_cpu_AVX_VNNI CPUID_INDEX_7_ECX_1
522#define index_cpu_AVX512_BF16 CPUID_INDEX_7_ECX_1
523#define index_cpu_FZLRM CPUID_INDEX_7_ECX_1
524#define index_cpu_FSRS CPUID_INDEX_7_ECX_1
525#define index_cpu_FSRCS CPUID_INDEX_7_ECX_1
526#define index_cpu_HRESET CPUID_INDEX_7_ECX_1
527#define index_cpu_LAM CPUID_INDEX_7_ECX_1
528
529/* CPUID_INDEX_19. */
530
531/* EBX. */
532#define index_cpu_AESKLE CPUID_INDEX_19
533#define index_cpu_WIDE_KL CPUID_INDEX_19
534
535/* CPUID_INDEX_1. */
536
537/* ECX. */
538#define reg_SSE3 ecx
539#define reg_PCLMULQDQ ecx
540#define reg_DTES64 ecx
541#define reg_MONITOR ecx
542#define reg_DS_CPL ecx
543#define reg_VMX ecx
544#define reg_SMX ecx
545#define reg_EIST ecx
546#define reg_TM2 ecx
547#define reg_SSSE3 ecx
548#define reg_CNXT_ID ecx
549#define reg_SDBG ecx
550#define reg_FMA ecx
551#define reg_CMPXCHG16B ecx
552#define reg_XTPRUPDCTRL ecx
553#define reg_PDCM ecx
554#define reg_INDEX_1_ECX_16 ecx
555#define reg_PCID ecx
556#define reg_DCA ecx
557#define reg_SSE4_1 ecx
558#define reg_SSE4_2 ecx
559#define reg_X2APIC ecx
560#define reg_MOVBE ecx
561#define reg_POPCNT ecx
562#define reg_TSC_DEADLINE ecx
563#define reg_AES ecx
564#define reg_XSAVE ecx
565#define reg_OSXSAVE ecx
566#define reg_AVX ecx
567#define reg_F16C ecx
568#define reg_RDRAND ecx
569#define reg_INDEX_1_ECX_31 ecx
570
571/* EDX. */
572#define reg_FPU edx
573#define reg_VME edx
574#define reg_DE edx
575#define reg_PSE edx
576#define reg_TSC edx
577#define reg_MSR edx
578#define reg_PAE edx
579#define reg_MCE edx
580#define reg_CX8 edx
581#define reg_APIC edx
582#define reg_INDEX_1_EDX_10 edx
583#define reg_SEP edx
584#define reg_MTRR edx
585#define reg_PGE edx
586#define reg_MCA edx
587#define reg_CMOV edx
588#define reg_PAT edx
589#define reg_PSE_36 edx
590#define reg_PSN edx
591#define reg_CLFSH edx
592#define reg_INDEX_1_EDX_20 edx
593#define reg_DS edx
594#define reg_ACPI edx
595#define reg_MMX edx
596#define reg_FXSR edx
597#define reg_SSE edx
598#define reg_SSE2 edx
599#define reg_SS edx
600#define reg_HTT edx
601#define reg_TM edx
602#define reg_INDEX_1_EDX_30 edx
603#define reg_PBE edx
604
605/* CPUID_INDEX_7. */
606
607/* EBX. */
608#define reg_FSGSBASE ebx
609#define reg_TSC_ADJUST ebx
610#define reg_SGX ebx
611#define reg_BMI1 ebx
612#define reg_HLE ebx
613#define reg_BMI2 ebx
614#define reg_AVX2 ebx
615#define reg_INDEX_7_EBX_6 ebx
616#define reg_SMEP ebx
617#define reg_ERMS ebx
618#define reg_INVPCID ebx
619#define reg_RTM ebx
620#define reg_RDT_M ebx
621#define reg_DEPR_FPU_CS_DS ebx
622#define reg_MPX ebx
623#define reg_RDT_A ebx
624#define reg_AVX512F ebx
625#define reg_AVX512DQ ebx
626#define reg_RDSEED ebx
627#define reg_ADX ebx
628#define reg_SMAP ebx
629#define reg_AVX512_IFMA ebx
630#define reg_INDEX_7_EBX_22 ebx
631#define reg_CLFLUSHOPT ebx
632#define reg_CLWB ebx
633#define reg_TRACE ebx
634#define reg_AVX512PF ebx
635#define reg_AVX512ER ebx
636#define reg_AVX512CD ebx
637#define reg_SHA ebx
638#define reg_AVX512BW ebx
639#define reg_AVX512VL ebx
640
641/* ECX. */
642#define reg_PREFETCHWT1 ecx
643#define reg_AVX512_VBMI ecx
644#define reg_UMIP ecx
645#define reg_PKU ecx
646#define reg_OSPKE ecx
647#define reg_WAITPKG ecx
648#define reg_AVX512_VBMI2 ecx
649#define reg_SHSTK ecx
650#define reg_GFNI ecx
651#define reg_VAES ecx
652#define reg_VPCLMULQDQ ecx
653#define reg_AVX512_VNNI ecx
654#define reg_AVX512_BITALG ecx
655#define reg_INDEX_7_ECX_13 ecx
656#define reg_AVX512_VPOPCNTDQ ecx
657#define reg_INDEX_7_ECX_15 ecx
658#define reg_INDEX_7_ECX_16 ecx
659#define reg_RDPID ecx
660#define reg_KL ecx
661#define reg_INDEX_7_ECX_24 ecx
662#define reg_CLDEMOTE ecx
663#define reg_INDEX_7_ECX_26 ecx
664#define reg_MOVDIRI ecx
665#define reg_MOVDIR64B ecx
666#define reg_ENQCMD ecx
667#define reg_SGX_LC ecx
668#define reg_PKS ecx
669
670/* EDX. */
671#define reg_INDEX_7_EDX_0 edx
672#define reg_INDEX_7_EDX_1 edx
673#define reg_AVX512_4VNNIW edx
674#define reg_AVX512_4FMAPS edx
675#define reg_FSRM edx
676#define reg_UINTR edx
677#define reg_INDEX_7_EDX_6 edx
678#define reg_INDEX_7_EDX_7 edx
679#define reg_AVX512_VP2INTERSECT edx
680#define reg_INDEX_7_EDX_9 edx
681#define reg_MD_CLEAR edx
682#define reg_INDEX_7_EDX_11 edx
683#define reg_INDEX_7_EDX_12 edx
684#define reg_INDEX_7_EDX_13 edx
685#define reg_SERIALIZE edx
686#define reg_HYBRID edx
687#define reg_TSXLDTRK edx
688#define reg_INDEX_7_EDX_17 edx
689#define reg_PCONFIG edx
690#define reg_INDEX_7_EDX_19 edx
691#define reg_IBT edx
692#define reg_INDEX_7_EDX_21 edx
693#define reg_AMX_BF16 edx
694#define reg_AVX512_FP16 edx
695#define reg_AMX_TILE edx
696#define reg_AMX_INT8 edx
697#define reg_IBRS_IBPB edx
698#define reg_STIBP edx
699#define reg_L1D_FLUSH edx
700#define reg_ARCH_CAPABILITIES edx
701#define reg_CORE_CAPABILITIES edx
702#define reg_SSBD edx
703
704/* CPUID_INDEX_80000001. */
705
706/* ECX. */
707#define reg_LAHF64_SAHF64 ecx
708#define reg_SVM ecx
709#define reg_LZCNT ecx
710#define reg_SSE4A ecx
711#define reg_PREFETCHW ecx
712#define reg_XOP ecx
713#define reg_LWP ecx
714#define reg_FMA4 ecx
715#define reg_TBM ecx
716
717/* EDX. */
718#define reg_SYSCALL_SYSRET edx
719#define reg_NX edx
720#define reg_PAGE1GB edx
721#define reg_RDTSCP edx
722#define reg_LM edx
723
724/* CPUID_INDEX_D_ECX_1. */
725
726/* EAX. */
727#define reg_XSAVEOPT eax
728#define reg_XSAVEC eax
729#define reg_XGETBV_ECX_1 eax
730#define reg_XSAVES eax
731#define reg_XFD eax
732
733/* CPUID_INDEX_80000007. */
734
735/* EDX. */
736#define reg_INVARIANT_TSC edx
737
738/* CPUID_INDEX_80000008. */
739
740/* EBX. */
741#define reg_WBNOINVD ebx
742
743/* CPUID_INDEX_7_ECX_1. */
744
745/* EAX. */
746#define reg_AVX_VNNI eax
747#define reg_AVX512_BF16 eax
748#define reg_FZLRM eax
749#define reg_FSRS eax
750#define reg_FSRCS eax
751#define reg_HRESET eax
752#define reg_LAM eax
753
754/* CPUID_INDEX_19. */
755
756/* EBX. */
757#define reg_AESKLE ebx
758#define reg_WIDE_KL ebx
759
760/* PREFERRED_FEATURE_INDEX_1. */
761#define bit_arch_I586 (1u << 0)
762#define bit_arch_I686 (1u << 1)
763#define bit_arch_Fast_Rep_String (1u << 2)
764#define bit_arch_Fast_Copy_Backward (1u << 3)
765#define bit_arch_Fast_Unaligned_Load (1u << 4)
766#define bit_arch_Fast_Unaligned_Copy (1u << 5)
767#define bit_arch_Slow_BSF (1u << 6)
768#define bit_arch_Slow_SSE4_2 (1u << 7)
769#define bit_arch_AVX_Fast_Unaligned_Load (1u << 8)
770#define bit_arch_Prefer_MAP_32BIT_EXEC (1u << 9)
771#define bit_arch_Prefer_PMINUB_for_stringop (1u << 10)
772#define bit_arch_Prefer_No_VZEROUPPER (1u << 11)
773#define bit_arch_Prefer_ERMS (1u << 12)
774#define bit_arch_Prefer_FSRM (1u << 13)
775#define bit_arch_Prefer_No_AVX512 (1u << 14)
776#define bit_arch_MathVec_Prefer_No_AVX512 (1u << 15)
777
778#define index_arch_Fast_Rep_String PREFERRED_FEATURE_INDEX_1
779#define index_arch_Fast_Copy_Backward PREFERRED_FEATURE_INDEX_1
780#define index_arch_Slow_BSF PREFERRED_FEATURE_INDEX_1
781#define index_arch_Fast_Unaligned_Load PREFERRED_FEATURE_INDEX_1
782#define index_arch_Prefer_PMINUB_for_stringop PREFERRED_FEATURE_INDEX_1
783#define index_arch_Fast_Unaligned_Copy PREFERRED_FEATURE_INDEX_1
784#define index_arch_I586 PREFERRED_FEATURE_INDEX_1
785#define index_arch_I686 PREFERRED_FEATURE_INDEX_1
786#define index_arch_Slow_SSE4_2 PREFERRED_FEATURE_INDEX_1
787#define index_arch_AVX_Fast_Unaligned_Load PREFERRED_FEATURE_INDEX_1
788#define index_arch_Prefer_MAP_32BIT_EXEC PREFERRED_FEATURE_INDEX_1
789#define index_arch_Prefer_No_VZEROUPPER PREFERRED_FEATURE_INDEX_1
790#define index_arch_Prefer_ERMS PREFERRED_FEATURE_INDEX_1
791#define index_arch_Prefer_No_AVX512 PREFERRED_FEATURE_INDEX_1
792#define index_arch_MathVec_Prefer_No_AVX512 PREFERRED_FEATURE_INDEX_1
793#define index_arch_Prefer_FSRM PREFERRED_FEATURE_INDEX_1
794
795/* XCR0 Feature flags. */
796#define bit_XMM_state (1u << 1)
797#define bit_YMM_state (1u << 2)
798#define bit_Opmask_state (1u << 5)
799#define bit_ZMM0_15_state (1u << 6)
800#define bit_ZMM16_31_state (1u << 7)
801#define bit_XTILECFG_state (1u << 17)
802#define bit_XTILEDATA_state (1u << 18)
803
804enum cpu_features_kind
805{
806 arch_kind_unknown = 0,
807 arch_kind_intel,
808 arch_kind_amd,
809 arch_kind_zhaoxin,
810 arch_kind_other
811};
812
813struct cpu_features_basic
814{
815 enum cpu_features_kind kind;
816 int max_cpuid;
817 unsigned int family;
818 unsigned int model;
819 unsigned int stepping;
820};
821
822struct cpuid_registers
823{
824 unsigned int eax;
825 unsigned int ebx;
826 unsigned int ecx;
827 unsigned int edx;
828};
829
830struct cpuid_feature_internal
831{
832 union
833 {
834 unsigned int cpuid_array[4];
835 struct cpuid_registers cpuid;
836 };
837 union
838 {
839 unsigned int usable_array[4];
840 struct cpuid_registers usable;
841 };
842};
843
844struct cpu_features
845{
846 struct cpu_features_basic basic;
847 struct cpuid_feature_internal features[CPUID_INDEX_MAX];
848 unsigned int preferred[PREFERRED_FEATURE_INDEX_MAX];
849 /* X86 micro-architecture ISA levels. */
850 unsigned int isa_1;
851 /* The state size for XSAVEC or XSAVE. The type must be unsigned long
852 int so that we use
853
854 sub xsave_state_size_offset(%rip) %RSP_LP
855
856 in _dl_runtime_resolve. */
857 unsigned long int xsave_state_size;
858 /* The full state size for XSAVE when XSAVEC is disabled by
859
860 GLIBC_TUNABLES=glibc.cpu.hwcaps=-XSAVEC
861 */
862 unsigned int xsave_state_full_size;
863 /* Data cache size for use in memory and string routines, typically
864 L1 size. */
865 unsigned long int data_cache_size;
866 /* Shared cache size for use in memory and string routines, typically
867 L2 or L3 size. */
868 unsigned long int shared_cache_size;
869 /* Threshold to use non temporal store. */
870 unsigned long int non_temporal_threshold;
871 /* Threshold to use "rep movsb". */
872 unsigned long int rep_movsb_threshold;
873 /* Threshold to use "rep stosb". */
874 unsigned long int rep_stosb_threshold;
875 /* _SC_LEVEL1_ICACHE_SIZE. */
876 unsigned long int level1_icache_size;
877 /* _SC_LEVEL1_DCACHE_SIZE. */
878 unsigned long int level1_dcache_size;
879 /* _SC_LEVEL1_DCACHE_ASSOC. */
880 unsigned long int level1_dcache_assoc;
881 /* _SC_LEVEL1_DCACHE_LINESIZE. */
882 unsigned long int level1_dcache_linesize;
883 /* _SC_LEVEL2_CACHE_ASSOC. */
884 unsigned long int level2_cache_size;
885 /* _SC_LEVEL2_DCACHE_ASSOC. */
886 unsigned long int level2_cache_assoc;
887 /* _SC_LEVEL2_CACHE_LINESIZE. */
888 unsigned long int level2_cache_linesize;
889 /* /_SC_LEVEL3_CACHE_SIZE. */
890 unsigned long int level3_cache_size;
891 /* _SC_LEVEL3_CACHE_ASSOC. */
892 unsigned long int level3_cache_assoc;
893 /* _SC_LEVEL3_CACHE_LINESIZE. */
894 unsigned long int level3_cache_linesize;
895 /* /_SC_LEVEL4_CACHE_SIZE. */
896 unsigned long int level4_cache_size;
897};
898
899/* Get a pointer to the CPU features structure. */
900extern const struct cpu_features *_dl_x86_get_cpu_features (void)
901 __attribute__ ((pure));
902
903#define __get_cpu_features() _dl_x86_get_cpu_features()
904
905#if defined (_LIBC) && !IS_IN (nonlib)
906/* Unused for x86. */
907# define INIT_ARCH()
908# define _dl_x86_get_cpu_features() (&GLRO(dl_x86_cpu_features))
909extern void _dl_x86_init_cpu_features (void) attribute_hidden;
910#endif
911
912#ifdef __x86_64__
913# define HAS_CPUID 1
914#elif (defined __i586__ || defined __pentium__ \
915 || defined __geode__ || defined __k6__)
916# define HAS_CPUID 1
917# define HAS_I586 1
918# define HAS_I686 HAS_ARCH_FEATURE (I686)
919#elif defined __i486__
920# define HAS_CPUID 0
921# define HAS_I586 HAS_ARCH_FEATURE (I586)
922# define HAS_I686 HAS_ARCH_FEATURE (I686)
923#else
924# define HAS_CPUID 1
925# define HAS_I586 1
926# define HAS_I686 1
927# endif
928
929#endif /* include/cpu-features.h */
930