| 1 | /* This file is part of the GNU C Library. |
| 2 | Copyright (C) 2008-2020 Free Software Foundation, Inc. |
| 3 | |
| 4 | The GNU C Library is free software; you can redistribute it and/or |
| 5 | modify it under the terms of the GNU Lesser General Public |
| 6 | License as published by the Free Software Foundation; either |
| 7 | version 2.1 of the License, or (at your option) any later version. |
| 8 | |
| 9 | The GNU C Library is distributed in the hope that it will be useful, |
| 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 12 | Lesser General Public License for more details. |
| 13 | |
| 14 | You should have received a copy of the GNU Lesser General Public |
| 15 | License along with the GNU C Library; if not, see |
| 16 | <https://www.gnu.org/licenses/>. */ |
| 17 | |
| 18 | #ifndef cpu_features_h |
| 19 | #define cpu_features_h |
| 20 | |
| 21 | enum |
| 22 | { |
| 23 | /* The integer bit array index for the first set of preferred feature |
| 24 | bits. */ |
| 25 | PREFERRED_FEATURE_INDEX_1 = 0, |
| 26 | /* The current maximum size of the feature integer bit array. */ |
| 27 | PREFERRED_FEATURE_INDEX_MAX |
| 28 | }; |
| 29 | |
| 30 | enum |
| 31 | { |
| 32 | COMMON_CPUID_INDEX_1 = 0, |
| 33 | COMMON_CPUID_INDEX_7, |
| 34 | COMMON_CPUID_INDEX_80000001, |
| 35 | COMMON_CPUID_INDEX_D_ECX_1, |
| 36 | COMMON_CPUID_INDEX_80000007, |
| 37 | COMMON_CPUID_INDEX_80000008, |
| 38 | COMMON_CPUID_INDEX_7_ECX_1, |
| 39 | /* Keep the following line at the end. */ |
| 40 | COMMON_CPUID_INDEX_MAX |
| 41 | }; |
| 42 | |
| 43 | struct cpuid_registers |
| 44 | { |
| 45 | unsigned int eax; |
| 46 | unsigned int ebx; |
| 47 | unsigned int ecx; |
| 48 | unsigned int edx; |
| 49 | }; |
| 50 | |
| 51 | struct cpuid_features |
| 52 | { |
| 53 | struct cpuid_registers cpuid; |
| 54 | struct cpuid_registers usable; |
| 55 | }; |
| 56 | |
| 57 | enum cpu_features_kind |
| 58 | { |
| 59 | arch_kind_unknown = 0, |
| 60 | arch_kind_intel, |
| 61 | arch_kind_amd, |
| 62 | arch_kind_zhaoxin, |
| 63 | arch_kind_other |
| 64 | }; |
| 65 | |
| 66 | struct cpu_features_basic |
| 67 | { |
| 68 | enum cpu_features_kind kind; |
| 69 | int max_cpuid; |
| 70 | unsigned int family; |
| 71 | unsigned int model; |
| 72 | unsigned int stepping; |
| 73 | }; |
| 74 | |
| 75 | struct cpu_features |
| 76 | { |
| 77 | struct cpu_features_basic basic; |
| 78 | struct cpuid_features features[COMMON_CPUID_INDEX_MAX]; |
| 79 | unsigned int preferred[PREFERRED_FEATURE_INDEX_MAX]; |
| 80 | /* The state size for XSAVEC or XSAVE. The type must be unsigned long |
| 81 | int so that we use |
| 82 | |
| 83 | sub xsave_state_size_offset(%rip) %RSP_LP |
| 84 | |
| 85 | in _dl_runtime_resolve. */ |
| 86 | unsigned long int xsave_state_size; |
| 87 | /* The full state size for XSAVE when XSAVEC is disabled by |
| 88 | |
| 89 | GLIBC_TUNABLES=glibc.cpu.hwcaps=-XSAVEC |
| 90 | */ |
| 91 | unsigned int xsave_state_full_size; |
| 92 | /* Data cache size for use in memory and string routines, typically |
| 93 | L1 size. */ |
| 94 | unsigned long int data_cache_size; |
| 95 | /* Shared cache size for use in memory and string routines, typically |
| 96 | L2 or L3 size. */ |
| 97 | unsigned long int shared_cache_size; |
| 98 | /* Threshold to use non temporal store. */ |
| 99 | unsigned long int non_temporal_threshold; |
| 100 | /* Threshold to use "rep movsb". */ |
| 101 | unsigned long int rep_movsb_threshold; |
| 102 | /* Threshold to use "rep stosb". */ |
| 103 | unsigned long int rep_stosb_threshold; |
| 104 | }; |
| 105 | |
| 106 | /* Used from outside of glibc to get access to the CPU features |
| 107 | structure. */ |
| 108 | extern const struct cpu_features *__get_cpu_features (void) |
| 109 | __attribute__ ((const)); |
| 110 | |
| 111 | /* Only used directly in cpu-features.c. */ |
| 112 | #define CPU_FEATURE_CHECK_P(ptr, name, check) \ |
| 113 | ((ptr->features[index_cpu_##name].check.reg_##name \ |
| 114 | & bit_cpu_##name) != 0) |
| 115 | #define CPU_FEATURE_SET(ptr, name) \ |
| 116 | ptr->features[index_cpu_##name].usable.reg_##name |= bit_cpu_##name; |
| 117 | #define CPU_FEATURE_UNSET(ptr, name) \ |
| 118 | ptr->features[index_cpu_##name].usable.reg_##name &= ~bit_cpu_##name; |
| 119 | #define CPU_FEATURE_SET_USABLE(ptr, name) \ |
| 120 | ptr->features[index_cpu_##name].usable.reg_##name \ |
| 121 | |= ptr->features[index_cpu_##name].cpuid.reg_##name & bit_cpu_##name; |
| 122 | #define CPU_FEATURE_PREFERRED_P(ptr, name) \ |
| 123 | ((ptr->preferred[index_arch_##name] & bit_arch_##name) != 0) |
| 124 | #define CPU_FEATURE_CPU_P(ptr, name) \ |
| 125 | CPU_FEATURE_CHECK_P (ptr, name, cpuid) |
| 126 | #define CPU_FEATURE_USABLE_P(ptr, name) \ |
| 127 | CPU_FEATURE_CHECK_P (ptr, name, usable) |
| 128 | |
| 129 | /* HAS_CPU_FEATURE evaluates to true if CPU supports the feature. */ |
| 130 | #define HAS_CPU_FEATURE(name) \ |
| 131 | CPU_FEATURE_CPU_P (__get_cpu_features (), name) |
| 132 | /* CPU_FEATURE_USABLE evaluates to true if the feature is usable. */ |
| 133 | #define CPU_FEATURE_USABLE(name) \ |
| 134 | CPU_FEATURE_USABLE_P (__get_cpu_features (), name) |
| 135 | /* CPU_FEATURE_PREFER evaluates to true if we prefer the feature at |
| 136 | runtime. */ |
| 137 | #define CPU_FEATURE_PREFERRED(name) \ |
| 138 | CPU_FEATURE_PREFERRED_P(__get_cpu_features (), name) |
| 139 | |
| 140 | #define CPU_FEATURES_CPU_P(ptr, name) \ |
| 141 | CPU_FEATURE_CPU_P (ptr, name) |
| 142 | #define CPU_FEATURES_ARCH_P(ptr, name) \ |
| 143 | CPU_FEATURE_PREFERRED_P (ptr, name) |
| 144 | #define HAS_ARCH_FEATURE(name) \ |
| 145 | CPU_FEATURE_PREFERRED (name) |
| 146 | |
| 147 | /* CPU features. */ |
| 148 | |
| 149 | /* COMMON_CPUID_INDEX_1. */ |
| 150 | |
| 151 | /* ECX. */ |
| 152 | #define bit_cpu_SSE3 (1u << 0) |
| 153 | #define bit_cpu_PCLMULQDQ (1u << 1) |
| 154 | #define bit_cpu_DTES64 (1u << 2) |
| 155 | #define bit_cpu_MONITOR (1u << 3) |
| 156 | #define bit_cpu_DS_CPL (1u << 4) |
| 157 | #define bit_cpu_VMX (1u << 5) |
| 158 | #define bit_cpu_SMX (1u << 6) |
| 159 | #define bit_cpu_EST (1u << 7) |
| 160 | #define bit_cpu_TM2 (1u << 8) |
| 161 | #define bit_cpu_SSSE3 (1u << 9) |
| 162 | #define bit_cpu_CNXT_ID (1u << 10) |
| 163 | #define bit_cpu_SDBG (1u << 11) |
| 164 | #define bit_cpu_FMA (1u << 12) |
| 165 | #define bit_cpu_CMPXCHG16B (1u << 13) |
| 166 | #define bit_cpu_XTPRUPDCTRL (1u << 14) |
| 167 | #define bit_cpu_PDCM (1u << 15) |
| 168 | #define bit_cpu_INDEX_1_ECX_16 (1u << 16) |
| 169 | #define bit_cpu_PCID (1u << 17) |
| 170 | #define bit_cpu_DCA (1u << 18) |
| 171 | #define bit_cpu_SSE4_1 (1u << 19) |
| 172 | #define bit_cpu_SSE4_2 (1u << 20) |
| 173 | #define bit_cpu_X2APIC (1u << 21) |
| 174 | #define bit_cpu_MOVBE (1u << 22) |
| 175 | #define bit_cpu_POPCNT (1u << 23) |
| 176 | #define bit_cpu_TSC_DEADLINE (1u << 24) |
| 177 | #define bit_cpu_AES (1u << 25) |
| 178 | #define bit_cpu_XSAVE (1u << 26) |
| 179 | #define bit_cpu_OSXSAVE (1u << 27) |
| 180 | #define bit_cpu_AVX (1u << 28) |
| 181 | #define bit_cpu_F16C (1u << 29) |
| 182 | #define bit_cpu_RDRAND (1u << 30) |
| 183 | #define bit_cpu_INDEX_1_ECX_31 (1u << 31) |
| 184 | |
| 185 | /* EDX. */ |
| 186 | #define bit_cpu_FPU (1u << 0) |
| 187 | #define bit_cpu_VME (1u << 1) |
| 188 | #define bit_cpu_DE (1u << 2) |
| 189 | #define bit_cpu_PSE (1u << 3) |
| 190 | #define bit_cpu_TSC (1u << 4) |
| 191 | #define bit_cpu_MSR (1u << 5) |
| 192 | #define bit_cpu_PAE (1u << 6) |
| 193 | #define bit_cpu_MCE (1u << 7) |
| 194 | #define bit_cpu_CX8 (1u << 8) |
| 195 | #define bit_cpu_APIC (1u << 9) |
| 196 | #define bit_cpu_INDEX_1_EDX_10 (1u << 10) |
| 197 | #define bit_cpu_SEP (1u << 11) |
| 198 | #define bit_cpu_MTRR (1u << 12) |
| 199 | #define bit_cpu_PGE (1u << 13) |
| 200 | #define bit_cpu_MCA (1u << 14) |
| 201 | #define bit_cpu_CMOV (1u << 15) |
| 202 | #define bit_cpu_PAT (1u << 16) |
| 203 | #define bit_cpu_PSE_36 (1u << 17) |
| 204 | #define bit_cpu_PSN (1u << 18) |
| 205 | #define bit_cpu_CLFSH (1u << 19) |
| 206 | #define bit_cpu_INDEX_1_EDX_20 (1u << 20) |
| 207 | #define bit_cpu_DS (1u << 21) |
| 208 | #define bit_cpu_ACPI (1u << 22) |
| 209 | #define bit_cpu_MMX (1u << 23) |
| 210 | #define bit_cpu_FXSR (1u << 24) |
| 211 | #define bit_cpu_SSE (1u << 25) |
| 212 | #define bit_cpu_SSE2 (1u << 26) |
| 213 | #define bit_cpu_SS (1u << 27) |
| 214 | #define bit_cpu_HTT (1u << 28) |
| 215 | #define bit_cpu_TM (1u << 29) |
| 216 | #define bit_cpu_INDEX_1_EDX_30 (1u << 30) |
| 217 | #define bit_cpu_PBE (1u << 31) |
| 218 | |
| 219 | /* COMMON_CPUID_INDEX_7. */ |
| 220 | |
| 221 | /* EBX. */ |
| 222 | #define bit_cpu_FSGSBASE (1u << 0) |
| 223 | #define bit_cpu_TSC_ADJUST (1u << 1) |
| 224 | #define bit_cpu_SGX (1u << 2) |
| 225 | #define bit_cpu_BMI1 (1u << 3) |
| 226 | #define bit_cpu_HLE (1u << 4) |
| 227 | #define bit_cpu_AVX2 (1u << 5) |
| 228 | #define bit_cpu_INDEX_7_EBX_6 (1u << 6) |
| 229 | #define bit_cpu_SMEP (1u << 7) |
| 230 | #define bit_cpu_BMI2 (1u << 8) |
| 231 | #define bit_cpu_ERMS (1u << 9) |
| 232 | #define bit_cpu_INVPCID (1u << 10) |
| 233 | #define bit_cpu_RTM (1u << 11) |
| 234 | #define bit_cpu_PQM (1u << 12) |
| 235 | #define bit_cpu_DEPR_FPU_CS_DS (1u << 13) |
| 236 | #define bit_cpu_MPX (1u << 14) |
| 237 | #define bit_cpu_PQE (1u << 15) |
| 238 | #define bit_cpu_AVX512F (1u << 16) |
| 239 | #define bit_cpu_AVX512DQ (1u << 17) |
| 240 | #define bit_cpu_RDSEED (1u << 18) |
| 241 | #define bit_cpu_ADX (1u << 19) |
| 242 | #define bit_cpu_SMAP (1u << 20) |
| 243 | #define bit_cpu_AVX512_IFMA (1u << 21) |
| 244 | #define bit_cpu_INDEX_7_EBX_22 (1u << 22) |
| 245 | #define bit_cpu_CLFLUSHOPT (1u << 23) |
| 246 | #define bit_cpu_CLWB (1u << 24) |
| 247 | #define bit_cpu_TRACE (1u << 25) |
| 248 | #define bit_cpu_AVX512PF (1u << 26) |
| 249 | #define bit_cpu_AVX512ER (1u << 27) |
| 250 | #define bit_cpu_AVX512CD (1u << 28) |
| 251 | #define bit_cpu_SHA (1u << 29) |
| 252 | #define bit_cpu_AVX512BW (1u << 30) |
| 253 | #define bit_cpu_AVX512VL (1u << 31) |
| 254 | |
| 255 | /* ECX. */ |
| 256 | #define bit_cpu_PREFETCHWT1 (1u << 0) |
| 257 | #define bit_cpu_AVX512_VBMI (1u << 1) |
| 258 | #define bit_cpu_UMIP (1u << 2) |
| 259 | #define bit_cpu_PKU (1u << 3) |
| 260 | #define bit_cpu_OSPKE (1u << 4) |
| 261 | #define bit_cpu_WAITPKG (1u << 5) |
| 262 | #define bit_cpu_AVX512_VBMI2 (1u << 6) |
| 263 | #define bit_cpu_SHSTK (1u << 7) |
| 264 | #define bit_cpu_GFNI (1u << 8) |
| 265 | #define bit_cpu_VAES (1u << 9) |
| 266 | #define bit_cpu_VPCLMULQDQ (1u << 10) |
| 267 | #define bit_cpu_AVX512_VNNI (1u << 11) |
| 268 | #define bit_cpu_AVX512_BITALG (1u << 12) |
| 269 | #define bit_cpu_INDEX_7_ECX_13 (1u << 13) |
| 270 | #define bit_cpu_AVX512_VPOPCNTDQ (1u << 14) |
| 271 | #define bit_cpu_INDEX_7_ECX_15 (1u << 15) |
| 272 | #define bit_cpu_INDEX_7_ECX_16 (1u << 16) |
| 273 | /* Note: Bits 17-21: The value of MAWAU used by the BNDLDX and BNDSTX |
| 274 | instructions in 64-bit mode. */ |
| 275 | #define bit_cpu_RDPID (1u << 22) |
| 276 | #define bit_cpu_INDEX_7_ECX_23 (1u << 23) |
| 277 | #define bit_cpu_INDEX_7_ECX_24 (1u << 24) |
| 278 | #define bit_cpu_CLDEMOTE (1u << 25) |
| 279 | #define bit_cpu_INDEX_7_ECX_26 (1u << 26) |
| 280 | #define bit_cpu_MOVDIRI (1u << 27) |
| 281 | #define bit_cpu_MOVDIR64B (1u << 28) |
| 282 | #define bit_cpu_ENQCMD (1u << 29) |
| 283 | #define bit_cpu_SGX_LC (1u << 30) |
| 284 | #define bit_cpu_PKS (1u << 31) |
| 285 | |
| 286 | /* EDX. */ |
| 287 | #define bit_cpu_INDEX_7_EDX_0 (1u << 0) |
| 288 | #define bit_cpu_INDEX_7_EDX_1 (1u << 1) |
| 289 | #define bit_cpu_AVX512_4VNNIW (1u << 2) |
| 290 | #define bit_cpu_AVX512_4FMAPS (1u << 3) |
| 291 | #define bit_cpu_FSRM (1u << 4) |
| 292 | #define bit_cpu_INDEX_7_EDX_5 (1u << 5) |
| 293 | #define bit_cpu_INDEX_7_EDX_6 (1u << 6) |
| 294 | #define bit_cpu_INDEX_7_EDX_7 (1u << 7) |
| 295 | #define bit_cpu_AVX512_VP2INTERSECT (1u << 8) |
| 296 | #define bit_cpu_INDEX_7_EDX_9 (1u << 9) |
| 297 | #define bit_cpu_MD_CLEAR (1u << 10) |
| 298 | #define bit_cpu_INDEX_7_EDX_11 (1u << 11) |
| 299 | #define bit_cpu_INDEX_7_EDX_12 (1u << 12) |
| 300 | #define bit_cpu_INDEX_7_EDX_13 (1u << 13) |
| 301 | #define bit_cpu_SERIALIZE (1u << 14) |
| 302 | #define bit_cpu_HYBRID (1u << 15) |
| 303 | #define bit_cpu_TSXLDTRK (1u << 16) |
| 304 | #define bit_cpu_INDEX_7_EDX_17 (1u << 17) |
| 305 | #define bit_cpu_PCONFIG (1u << 18) |
| 306 | #define bit_cpu_INDEX_7_EDX_19 (1u << 19) |
| 307 | #define bit_cpu_IBT (1u << 20) |
| 308 | #define bit_cpu_INDEX_7_EDX_21 (1u << 21) |
| 309 | #define bit_cpu_AMX_BF16 (1u << 22) |
| 310 | #define bit_cpu_INDEX_7_EDX_23 (1u << 23) |
| 311 | #define bit_cpu_AMX_TILE (1u << 24) |
| 312 | #define bit_cpu_AMX_INT8 (1u << 25) |
| 313 | #define bit_cpu_IBRS_IBPB (1u << 26) |
| 314 | #define bit_cpu_STIBP (1u << 27) |
| 315 | #define bit_cpu_L1D_FLUSH (1u << 28) |
| 316 | #define bit_cpu_ARCH_CAPABILITIES (1u << 29) |
| 317 | #define bit_cpu_CORE_CAPABILITIES (1u << 30) |
| 318 | #define bit_cpu_SSBD (1u << 31) |
| 319 | |
| 320 | /* COMMON_CPUID_INDEX_80000001. */ |
| 321 | |
| 322 | /* ECX. */ |
| 323 | #define bit_cpu_LAHF64_SAHF64 (1u << 0) |
| 324 | #define bit_cpu_SVM (1u << 2) |
| 325 | #define bit_cpu_LZCNT (1u << 5) |
| 326 | #define bit_cpu_SSE4A (1u << 6) |
| 327 | #define bit_cpu_PREFETCHW (1u << 8) |
| 328 | #define bit_cpu_XOP (1u << 11) |
| 329 | #define bit_cpu_LWP (1u << 15) |
| 330 | #define bit_cpu_FMA4 (1u << 16) |
| 331 | #define bit_cpu_TBM (1u << 21) |
| 332 | |
| 333 | /* EDX. */ |
| 334 | #define bit_cpu_SYSCALL_SYSRET (1u << 11) |
| 335 | #define bit_cpu_NX (1u << 20) |
| 336 | #define bit_cpu_PAGE1GB (1u << 26) |
| 337 | #define bit_cpu_RDTSCP (1u << 27) |
| 338 | #define bit_cpu_LM (1u << 29) |
| 339 | |
| 340 | /* COMMON_CPUID_INDEX_D_ECX_1. */ |
| 341 | |
| 342 | /* EAX. */ |
| 343 | #define bit_cpu_XSAVEOPT (1u << 0) |
| 344 | #define bit_cpu_XSAVEC (1u << 1) |
| 345 | #define bit_cpu_XGETBV_ECX_1 (1u << 2) |
| 346 | #define bit_cpu_XSAVES (1u << 3) |
| 347 | #define bit_cpu_XFD (1u << 4) |
| 348 | |
| 349 | /* COMMON_CPUID_INDEX_80000007. */ |
| 350 | |
| 351 | /* EDX. */ |
| 352 | #define bit_cpu_INVARIANT_TSC (1u << 8) |
| 353 | |
| 354 | /* COMMON_CPUID_INDEX_80000008. */ |
| 355 | |
| 356 | /* EBX. */ |
| 357 | #define bit_cpu_WBNOINVD (1u << 9) |
| 358 | |
| 359 | /* COMMON_CPUID_INDEX_7_ECX_1. */ |
| 360 | |
| 361 | /* EAX. */ |
| 362 | #define bit_cpu_AVX512_BF16 (1u << 5) |
| 363 | |
| 364 | /* COMMON_CPUID_INDEX_1. */ |
| 365 | |
| 366 | /* ECX. */ |
| 367 | #define index_cpu_SSE3 COMMON_CPUID_INDEX_1 |
| 368 | #define index_cpu_PCLMULQDQ COMMON_CPUID_INDEX_1 |
| 369 | #define index_cpu_DTES64 COMMON_CPUID_INDEX_1 |
| 370 | #define index_cpu_MONITOR COMMON_CPUID_INDEX_1 |
| 371 | #define index_cpu_DS_CPL COMMON_CPUID_INDEX_1 |
| 372 | #define index_cpu_VMX COMMON_CPUID_INDEX_1 |
| 373 | #define index_cpu_SMX COMMON_CPUID_INDEX_1 |
| 374 | #define index_cpu_EST COMMON_CPUID_INDEX_1 |
| 375 | #define index_cpu_TM2 COMMON_CPUID_INDEX_1 |
| 376 | #define index_cpu_SSSE3 COMMON_CPUID_INDEX_1 |
| 377 | #define index_cpu_CNXT_ID COMMON_CPUID_INDEX_1 |
| 378 | #define index_cpu_SDBG COMMON_CPUID_INDEX_1 |
| 379 | #define index_cpu_FMA COMMON_CPUID_INDEX_1 |
| 380 | #define index_cpu_CMPXCHG16B COMMON_CPUID_INDEX_1 |
| 381 | #define index_cpu_XTPRUPDCTRL COMMON_CPUID_INDEX_1 |
| 382 | #define index_cpu_PDCM COMMON_CPUID_INDEX_1 |
| 383 | #define index_cpu_INDEX_1_ECX_16 COMMON_CPUID_INDEX_1 |
| 384 | #define index_cpu_PCID COMMON_CPUID_INDEX_1 |
| 385 | #define index_cpu_DCA COMMON_CPUID_INDEX_1 |
| 386 | #define index_cpu_SSE4_1 COMMON_CPUID_INDEX_1 |
| 387 | #define index_cpu_SSE4_2 COMMON_CPUID_INDEX_1 |
| 388 | #define index_cpu_X2APIC COMMON_CPUID_INDEX_1 |
| 389 | #define index_cpu_MOVBE COMMON_CPUID_INDEX_1 |
| 390 | #define index_cpu_POPCNT COMMON_CPUID_INDEX_1 |
| 391 | #define index_cpu_TSC_DEADLINE COMMON_CPUID_INDEX_1 |
| 392 | #define index_cpu_AES COMMON_CPUID_INDEX_1 |
| 393 | #define index_cpu_XSAVE COMMON_CPUID_INDEX_1 |
| 394 | #define index_cpu_OSXSAVE COMMON_CPUID_INDEX_1 |
| 395 | #define index_cpu_AVX COMMON_CPUID_INDEX_1 |
| 396 | #define index_cpu_F16C COMMON_CPUID_INDEX_1 |
| 397 | #define index_cpu_RDRAND COMMON_CPUID_INDEX_1 |
| 398 | #define index_cpu_INDEX_1_ECX_31 COMMON_CPUID_INDEX_1 |
| 399 | |
| 400 | /* ECX. */ |
| 401 | #define index_cpu_FPU COMMON_CPUID_INDEX_1 |
| 402 | #define index_cpu_VME COMMON_CPUID_INDEX_1 |
| 403 | #define index_cpu_DE COMMON_CPUID_INDEX_1 |
| 404 | #define index_cpu_PSE COMMON_CPUID_INDEX_1 |
| 405 | #define index_cpu_TSC COMMON_CPUID_INDEX_1 |
| 406 | #define index_cpu_MSR COMMON_CPUID_INDEX_1 |
| 407 | #define index_cpu_PAE COMMON_CPUID_INDEX_1 |
| 408 | #define index_cpu_MCE COMMON_CPUID_INDEX_1 |
| 409 | #define index_cpu_CX8 COMMON_CPUID_INDEX_1 |
| 410 | #define index_cpu_APIC COMMON_CPUID_INDEX_1 |
| 411 | #define index_cpu_INDEX_1_EDX_10 COMMON_CPUID_INDEX_1 |
| 412 | #define index_cpu_SEP COMMON_CPUID_INDEX_1 |
| 413 | #define index_cpu_MTRR COMMON_CPUID_INDEX_1 |
| 414 | #define index_cpu_PGE COMMON_CPUID_INDEX_1 |
| 415 | #define index_cpu_MCA COMMON_CPUID_INDEX_1 |
| 416 | #define index_cpu_CMOV COMMON_CPUID_INDEX_1 |
| 417 | #define index_cpu_PAT COMMON_CPUID_INDEX_1 |
| 418 | #define index_cpu_PSE_36 COMMON_CPUID_INDEX_1 |
| 419 | #define index_cpu_PSN COMMON_CPUID_INDEX_1 |
| 420 | #define index_cpu_CLFSH COMMON_CPUID_INDEX_1 |
| 421 | #define index_cpu_INDEX_1_EDX_20 COMMON_CPUID_INDEX_1 |
| 422 | #define index_cpu_DS COMMON_CPUID_INDEX_1 |
| 423 | #define index_cpu_ACPI COMMON_CPUID_INDEX_1 |
| 424 | #define index_cpu_MMX COMMON_CPUID_INDEX_1 |
| 425 | #define index_cpu_FXSR COMMON_CPUID_INDEX_1 |
| 426 | #define index_cpu_SSE COMMON_CPUID_INDEX_1 |
| 427 | #define index_cpu_SSE2 COMMON_CPUID_INDEX_1 |
| 428 | #define index_cpu_SS COMMON_CPUID_INDEX_1 |
| 429 | #define index_cpu_HTT COMMON_CPUID_INDEX_1 |
| 430 | #define index_cpu_TM COMMON_CPUID_INDEX_1 |
| 431 | #define index_cpu_INDEX_1_EDX_30 COMMON_CPUID_INDEX_1 |
| 432 | #define index_cpu_PBE COMMON_CPUID_INDEX_1 |
| 433 | |
| 434 | /* COMMON_CPUID_INDEX_7. */ |
| 435 | |
| 436 | /* EBX. */ |
| 437 | #define index_cpu_FSGSBASE COMMON_CPUID_INDEX_7 |
| 438 | #define index_cpu_TSC_ADJUST COMMON_CPUID_INDEX_7 |
| 439 | #define index_cpu_SGX COMMON_CPUID_INDEX_7 |
| 440 | #define index_cpu_BMI1 COMMON_CPUID_INDEX_7 |
| 441 | #define index_cpu_HLE COMMON_CPUID_INDEX_7 |
| 442 | #define index_cpu_AVX2 COMMON_CPUID_INDEX_7 |
| 443 | #define index_cpu_INDEX_7_EBX_6 COMMON_CPUID_INDEX_7 |
| 444 | #define index_cpu_SMEP COMMON_CPUID_INDEX_7 |
| 445 | #define index_cpu_BMI2 COMMON_CPUID_INDEX_7 |
| 446 | #define index_cpu_ERMS COMMON_CPUID_INDEX_7 |
| 447 | #define index_cpu_INVPCID COMMON_CPUID_INDEX_7 |
| 448 | #define index_cpu_RTM COMMON_CPUID_INDEX_7 |
| 449 | #define index_cpu_PQM COMMON_CPUID_INDEX_7 |
| 450 | #define index_cpu_DEPR_FPU_CS_DS COMMON_CPUID_INDEX_7 |
| 451 | #define index_cpu_MPX COMMON_CPUID_INDEX_7 |
| 452 | #define index_cpu_PQE COMMON_CPUID_INDEX_7 |
| 453 | #define index_cpu_AVX512F COMMON_CPUID_INDEX_7 |
| 454 | #define index_cpu_AVX512DQ COMMON_CPUID_INDEX_7 |
| 455 | #define index_cpu_RDSEED COMMON_CPUID_INDEX_7 |
| 456 | #define index_cpu_ADX COMMON_CPUID_INDEX_7 |
| 457 | #define index_cpu_SMAP COMMON_CPUID_INDEX_7 |
| 458 | #define index_cpu_AVX512_IFMA COMMON_CPUID_INDEX_7 |
| 459 | #define index_cpu_INDEX_7_EBX_22 COMMON_CPUID_INDEX_7 |
| 460 | #define index_cpu_CLFLUSHOPT COMMON_CPUID_INDEX_7 |
| 461 | #define index_cpu_CLWB COMMON_CPUID_INDEX_7 |
| 462 | #define index_cpu_TRACE COMMON_CPUID_INDEX_7 |
| 463 | #define index_cpu_AVX512PF COMMON_CPUID_INDEX_7 |
| 464 | #define index_cpu_AVX512ER COMMON_CPUID_INDEX_7 |
| 465 | #define index_cpu_AVX512CD COMMON_CPUID_INDEX_7 |
| 466 | #define index_cpu_SHA COMMON_CPUID_INDEX_7 |
| 467 | #define index_cpu_AVX512BW COMMON_CPUID_INDEX_7 |
| 468 | #define index_cpu_AVX512VL COMMON_CPUID_INDEX_7 |
| 469 | |
| 470 | /* ECX. */ |
| 471 | #define index_cpu_PREFETCHWT1 COMMON_CPUID_INDEX_7 |
| 472 | #define index_cpu_AVX512_VBMI COMMON_CPUID_INDEX_7 |
| 473 | #define index_cpu_UMIP COMMON_CPUID_INDEX_7 |
| 474 | #define index_cpu_PKU COMMON_CPUID_INDEX_7 |
| 475 | #define index_cpu_OSPKE COMMON_CPUID_INDEX_7 |
| 476 | #define index_cpu_WAITPKG COMMON_CPUID_INDEX_7 |
| 477 | #define index_cpu_AVX512_VBMI2 COMMON_CPUID_INDEX_7 |
| 478 | #define index_cpu_SHSTK COMMON_CPUID_INDEX_7 |
| 479 | #define index_cpu_GFNI COMMON_CPUID_INDEX_7 |
| 480 | #define index_cpu_VAES COMMON_CPUID_INDEX_7 |
| 481 | #define index_cpu_VPCLMULQDQ COMMON_CPUID_INDEX_7 |
| 482 | #define index_cpu_AVX512_VNNI COMMON_CPUID_INDEX_7 |
| 483 | #define index_cpu_AVX512_BITALG COMMON_CPUID_INDEX_7 |
| 484 | #define index_cpu_INDEX_7_ECX_13 COMMON_CPUID_INDEX_7 |
| 485 | #define index_cpu_AVX512_VPOPCNTDQ COMMON_CPUID_INDEX_7 |
| 486 | #define index_cpu_INDEX_7_ECX_15 COMMON_CPUID_INDEX_7 |
| 487 | #define index_cpu_INDEX_7_ECX_16 COMMON_CPUID_INDEX_7 |
| 488 | #define index_cpu_RDPID COMMON_CPUID_INDEX_7 |
| 489 | #define index_cpu_INDEX_7_ECX_23 COMMON_CPUID_INDEX_7 |
| 490 | #define index_cpu_INDEX_7_ECX_24 COMMON_CPUID_INDEX_7 |
| 491 | #define index_cpu_CLDEMOTE COMMON_CPUID_INDEX_7 |
| 492 | #define index_cpu_INDEX_7_ECX_26 COMMON_CPUID_INDEX_7 |
| 493 | #define index_cpu_MOVDIRI COMMON_CPUID_INDEX_7 |
| 494 | #define index_cpu_MOVDIR64B COMMON_CPUID_INDEX_7 |
| 495 | #define index_cpu_ENQCMD COMMON_CPUID_INDEX_7 |
| 496 | #define index_cpu_SGX_LC COMMON_CPUID_INDEX_7 |
| 497 | #define index_cpu_PKS COMMON_CPUID_INDEX_7 |
| 498 | |
| 499 | /* EDX. */ |
| 500 | #define index_cpu_INDEX_7_EDX_0 COMMON_CPUID_INDEX_7 |
| 501 | #define index_cpu_INDEX_7_EDX_1 COMMON_CPUID_INDEX_7 |
| 502 | #define index_cpu_AVX512_4VNNIW COMMON_CPUID_INDEX_7 |
| 503 | #define index_cpu_AVX512_4FMAPS COMMON_CPUID_INDEX_7 |
| 504 | #define index_cpu_FSRM COMMON_CPUID_INDEX_7 |
| 505 | #define index_cpu_INDEX_7_EDX_5 COMMON_CPUID_INDEX_7 |
| 506 | #define index_cpu_INDEX_7_EDX_6 COMMON_CPUID_INDEX_7 |
| 507 | #define index_cpu_INDEX_7_EDX_7 COMMON_CPUID_INDEX_7 |
| 508 | #define index_cpu_AVX512_VP2INTERSECT COMMON_CPUID_INDEX_7 |
| 509 | #define index_cpu_INDEX_7_EDX_9 COMMON_CPUID_INDEX_7 |
| 510 | #define index_cpu_MD_CLEAR COMMON_CPUID_INDEX_7 |
| 511 | #define index_cpu_INDEX_7_EDX_11 COMMON_CPUID_INDEX_7 |
| 512 | #define index_cpu_INDEX_7_EDX_12 COMMON_CPUID_INDEX_7 |
| 513 | #define index_cpu_INDEX_7_EDX_13 COMMON_CPUID_INDEX_7 |
| 514 | #define index_cpu_SERIALIZE COMMON_CPUID_INDEX_7 |
| 515 | #define index_cpu_HYBRID COMMON_CPUID_INDEX_7 |
| 516 | #define index_cpu_TSXLDTRK COMMON_CPUID_INDEX_7 |
| 517 | #define index_cpu_INDEX_7_EDX_17 COMMON_CPUID_INDEX_7 |
| 518 | #define index_cpu_PCONFIG COMMON_CPUID_INDEX_7 |
| 519 | #define index_cpu_INDEX_7_EDX_19 COMMON_CPUID_INDEX_7 |
| 520 | #define index_cpu_IBT COMMON_CPUID_INDEX_7 |
| 521 | #define index_cpu_INDEX_7_EDX_21 COMMON_CPUID_INDEX_7 |
| 522 | #define index_cpu_AMX_BF16 COMMON_CPUID_INDEX_7 |
| 523 | #define index_cpu_INDEX_7_EDX_23 COMMON_CPUID_INDEX_7 |
| 524 | #define index_cpu_AMX_TILE COMMON_CPUID_INDEX_7 |
| 525 | #define index_cpu_AMX_INT8 COMMON_CPUID_INDEX_7 |
| 526 | #define index_cpu_IBRS_IBPB COMMON_CPUID_INDEX_7 |
| 527 | #define index_cpu_STIBP COMMON_CPUID_INDEX_7 |
| 528 | #define index_cpu_L1D_FLUSH COMMON_CPUID_INDEX_7 |
| 529 | #define index_cpu_ARCH_CAPABILITIES COMMON_CPUID_INDEX_7 |
| 530 | #define index_cpu_CORE_CAPABILITIES COMMON_CPUID_INDEX_7 |
| 531 | #define index_cpu_SSBD COMMON_CPUID_INDEX_7 |
| 532 | |
| 533 | /* COMMON_CPUID_INDEX_80000001. */ |
| 534 | |
| 535 | /* ECX. */ |
| 536 | #define index_cpu_LAHF64_SAHF64 COMMON_CPUID_INDEX_80000001 |
| 537 | #define index_cpu_SVM COMMON_CPUID_INDEX_80000001 |
| 538 | #define index_cpu_LZCNT COMMON_CPUID_INDEX_80000001 |
| 539 | #define index_cpu_SSE4A COMMON_CPUID_INDEX_80000001 |
| 540 | #define index_cpu_PREFETCHW COMMON_CPUID_INDEX_80000001 |
| 541 | #define index_cpu_XOP COMMON_CPUID_INDEX_80000001 |
| 542 | #define index_cpu_LWP COMMON_CPUID_INDEX_80000001 |
| 543 | #define index_cpu_FMA4 COMMON_CPUID_INDEX_80000001 |
| 544 | #define index_cpu_TBM COMMON_CPUID_INDEX_80000001 |
| 545 | |
| 546 | /* EDX. */ |
| 547 | #define index_cpu_SYSCALL_SYSRET COMMON_CPUID_INDEX_80000001 |
| 548 | #define index_cpu_NX COMMON_CPUID_INDEX_80000001 |
| 549 | #define index_cpu_PAGE1GB COMMON_CPUID_INDEX_80000001 |
| 550 | #define index_cpu_RDTSCP COMMON_CPUID_INDEX_80000001 |
| 551 | #define index_cpu_LM COMMON_CPUID_INDEX_80000001 |
| 552 | |
| 553 | /* COMMON_CPUID_INDEX_D_ECX_1. */ |
| 554 | |
| 555 | /* EAX. */ |
| 556 | #define index_cpu_XSAVEOPT COMMON_CPUID_INDEX_D_ECX_1 |
| 557 | #define index_cpu_XSAVEC COMMON_CPUID_INDEX_D_ECX_1 |
| 558 | #define index_cpu_XGETBV_ECX_1 COMMON_CPUID_INDEX_D_ECX_1 |
| 559 | #define index_cpu_XSAVES COMMON_CPUID_INDEX_D_ECX_1 |
| 560 | #define index_cpu_XFD COMMON_CPUID_INDEX_D_ECX_1 |
| 561 | |
| 562 | /* COMMON_CPUID_INDEX_80000007. */ |
| 563 | |
| 564 | /* EDX. */ |
| 565 | #define index_cpu_INVARIANT_TSC COMMON_CPUID_INDEX_80000007 |
| 566 | |
| 567 | /* COMMON_CPUID_INDEX_80000008. */ |
| 568 | |
| 569 | /* EBX. */ |
| 570 | #define index_cpu_WBNOINVD COMMON_CPUID_INDEX_80000008 |
| 571 | |
| 572 | /* COMMON_CPUID_INDEX_7_ECX_1. */ |
| 573 | |
| 574 | /* EAX. */ |
| 575 | #define index_cpu_AVX512_BF16 COMMON_CPUID_INDEX_7_ECX_1 |
| 576 | |
| 577 | /* COMMON_CPUID_INDEX_1. */ |
| 578 | |
| 579 | /* ECX. */ |
| 580 | #define reg_SSE3 ecx |
| 581 | #define reg_PCLMULQDQ ecx |
| 582 | #define reg_DTES64 ecx |
| 583 | #define reg_MONITOR ecx |
| 584 | #define reg_DS_CPL ecx |
| 585 | #define reg_VMX ecx |
| 586 | #define reg_SMX ecx |
| 587 | #define reg_EST ecx |
| 588 | #define reg_TM2 ecx |
| 589 | #define reg_SSSE3 ecx |
| 590 | #define reg_CNXT_ID ecx |
| 591 | #define reg_SDBG ecx |
| 592 | #define reg_FMA ecx |
| 593 | #define reg_CMPXCHG16B ecx |
| 594 | #define reg_XTPRUPDCTRL ecx |
| 595 | #define reg_PDCM ecx |
| 596 | #define reg_INDEX_1_ECX_16 ecx |
| 597 | #define reg_PCID ecx |
| 598 | #define reg_DCA ecx |
| 599 | #define reg_SSE4_1 ecx |
| 600 | #define reg_SSE4_2 ecx |
| 601 | #define reg_X2APIC ecx |
| 602 | #define reg_MOVBE ecx |
| 603 | #define reg_POPCNT ecx |
| 604 | #define reg_TSC_DEADLINE ecx |
| 605 | #define reg_AES ecx |
| 606 | #define reg_XSAVE ecx |
| 607 | #define reg_OSXSAVE ecx |
| 608 | #define reg_AVX ecx |
| 609 | #define reg_F16C ecx |
| 610 | #define reg_RDRAND ecx |
| 611 | #define reg_INDEX_1_ECX_31 ecx |
| 612 | |
| 613 | /* EDX. */ |
| 614 | #define reg_FPU edx |
| 615 | #define reg_VME edx |
| 616 | #define reg_DE edx |
| 617 | #define reg_PSE edx |
| 618 | #define reg_TSC edx |
| 619 | #define reg_MSR edx |
| 620 | #define reg_PAE edx |
| 621 | #define reg_MCE edx |
| 622 | #define reg_CX8 edx |
| 623 | #define reg_APIC edx |
| 624 | #define reg_INDEX_1_EDX_10 edx |
| 625 | #define reg_SEP edx |
| 626 | #define reg_MTRR edx |
| 627 | #define reg_PGE edx |
| 628 | #define reg_MCA edx |
| 629 | #define reg_CMOV edx |
| 630 | #define reg_PAT edx |
| 631 | #define reg_PSE_36 edx |
| 632 | #define reg_PSN edx |
| 633 | #define reg_CLFSH edx |
| 634 | #define reg_INDEX_1_EDX_20 edx |
| 635 | #define reg_DS edx |
| 636 | #define reg_ACPI edx |
| 637 | #define reg_MMX edx |
| 638 | #define reg_FXSR edx |
| 639 | #define reg_SSE edx |
| 640 | #define reg_SSE2 edx |
| 641 | #define reg_SS edx |
| 642 | #define reg_HTT edx |
| 643 | #define reg_TM edx |
| 644 | #define reg_INDEX_1_EDX_30 edx |
| 645 | #define reg_PBE edx |
| 646 | |
| 647 | /* COMMON_CPUID_INDEX_7. */ |
| 648 | |
| 649 | /* EBX. */ |
| 650 | #define reg_FSGSBASE ebx |
| 651 | #define reg_TSC_ADJUST ebx |
| 652 | #define reg_SGX ebx |
| 653 | #define reg_BMI1 ebx |
| 654 | #define reg_HLE ebx |
| 655 | #define reg_BMI2 ebx |
| 656 | #define reg_AVX2 ebx |
| 657 | #define reg_INDEX_7_EBX_6 ebx |
| 658 | #define reg_SMEP ebx |
| 659 | #define reg_ERMS ebx |
| 660 | #define reg_INVPCID ebx |
| 661 | #define reg_RTM ebx |
| 662 | #define reg_PQM ebx |
| 663 | #define reg_DEPR_FPU_CS_DS ebx |
| 664 | #define reg_MPX ebx |
| 665 | #define reg_PQE ebx |
| 666 | #define reg_AVX512F ebx |
| 667 | #define reg_AVX512DQ ebx |
| 668 | #define reg_RDSEED ebx |
| 669 | #define reg_ADX ebx |
| 670 | #define reg_SMAP ebx |
| 671 | #define reg_AVX512_IFMA ebx |
| 672 | #define reg_INDEX_7_EBX_22 ebx |
| 673 | #define reg_CLFLUSHOPT ebx |
| 674 | #define reg_CLWB ebx |
| 675 | #define reg_TRACE ebx |
| 676 | #define reg_AVX512PF ebx |
| 677 | #define reg_AVX512ER ebx |
| 678 | #define reg_AVX512CD ebx |
| 679 | #define reg_SHA ebx |
| 680 | #define reg_AVX512BW ebx |
| 681 | #define reg_AVX512VL ebx |
| 682 | |
| 683 | /* ECX. */ |
| 684 | #define reg_PREFETCHWT1 ecx |
| 685 | #define reg_AVX512_VBMI ecx |
| 686 | #define reg_UMIP ecx |
| 687 | #define reg_PKU ecx |
| 688 | #define reg_OSPKE ecx |
| 689 | #define reg_WAITPKG ecx |
| 690 | #define reg_AVX512_VBMI2 ecx |
| 691 | #define reg_SHSTK ecx |
| 692 | #define reg_GFNI ecx |
| 693 | #define reg_VAES ecx |
| 694 | #define reg_VPCLMULQDQ ecx |
| 695 | #define reg_AVX512_VNNI ecx |
| 696 | #define reg_AVX512_BITALG ecx |
| 697 | #define reg_INDEX_7_ECX_13 ecx |
| 698 | #define reg_AVX512_VPOPCNTDQ ecx |
| 699 | #define reg_INDEX_7_ECX_15 ecx |
| 700 | #define reg_INDEX_7_ECX_16 ecx |
| 701 | #define reg_RDPID ecx |
| 702 | #define reg_INDEX_7_ECX_23 ecx |
| 703 | #define reg_INDEX_7_ECX_24 ecx |
| 704 | #define reg_CLDEMOTE ecx |
| 705 | #define reg_INDEX_7_ECX_26 ecx |
| 706 | #define reg_MOVDIRI ecx |
| 707 | #define reg_MOVDIR64B ecx |
| 708 | #define reg_ENQCMD ecx |
| 709 | #define reg_SGX_LC ecx |
| 710 | #define reg_PKS ecx |
| 711 | |
| 712 | /* EDX. */ |
| 713 | #define reg_INDEX_7_EDX_0 edx |
| 714 | #define reg_INDEX_7_EDX_1 edx |
| 715 | #define reg_AVX512_4VNNIW edx |
| 716 | #define reg_AVX512_4FMAPS edx |
| 717 | #define reg_FSRM edx |
| 718 | #define reg_INDEX_7_EDX_5 edx |
| 719 | #define reg_INDEX_7_EDX_6 edx |
| 720 | #define reg_INDEX_7_EDX_7 edx |
| 721 | #define reg_AVX512_VP2INTERSECT edx |
| 722 | #define reg_INDEX_7_EDX_9 edx |
| 723 | #define reg_MD_CLEAR edx |
| 724 | #define reg_INDEX_7_EDX_11 edx |
| 725 | #define reg_INDEX_7_EDX_12 edx |
| 726 | #define reg_INDEX_7_EDX_13 edx |
| 727 | #define reg_SERIALIZE edx |
| 728 | #define reg_HYBRID edx |
| 729 | #define reg_TSXLDTRK edx |
| 730 | #define reg_INDEX_7_EDX_17 edx |
| 731 | #define reg_PCONFIG edx |
| 732 | #define reg_INDEX_7_EDX_19 edx |
| 733 | #define reg_IBT edx |
| 734 | #define reg_INDEX_7_EDX_21 edx |
| 735 | #define reg_AMX_BF16 edx |
| 736 | #define reg_INDEX_7_EDX_23 edx |
| 737 | #define reg_AMX_TILE edx |
| 738 | #define reg_AMX_INT8 edx |
| 739 | #define reg_IBRS_IBPB edx |
| 740 | #define reg_STIBP edx |
| 741 | #define reg_L1D_FLUSH edx |
| 742 | #define reg_ARCH_CAPABILITIES edx |
| 743 | #define reg_CORE_CAPABILITIES edx |
| 744 | #define reg_SSBD edx |
| 745 | |
| 746 | /* COMMON_CPUID_INDEX_80000001. */ |
| 747 | |
| 748 | /* ECX. */ |
| 749 | #define reg_LAHF64_SAHF64 ecx |
| 750 | #define reg_SVM ecx |
| 751 | #define reg_LZCNT ecx |
| 752 | #define reg_SSE4A ecx |
| 753 | #define reg_PREFETCHW ecx |
| 754 | #define reg_XOP ecx |
| 755 | #define reg_LWP ecx |
| 756 | #define reg_FMA4 ecx |
| 757 | #define reg_TBM ecx |
| 758 | |
| 759 | /* EDX. */ |
| 760 | #define reg_SYSCALL_SYSRET edx |
| 761 | #define reg_NX edx |
| 762 | #define reg_PAGE1GB edx |
| 763 | #define reg_RDTSCP edx |
| 764 | #define reg_LM edx |
| 765 | |
| 766 | /* COMMON_CPUID_INDEX_D_ECX_1. */ |
| 767 | |
| 768 | /* EAX. */ |
| 769 | #define reg_XSAVEOPT eax |
| 770 | #define reg_XSAVEC eax |
| 771 | #define reg_XGETBV_ECX_1 eax |
| 772 | #define reg_XSAVES eax |
| 773 | #define reg_XFD eax |
| 774 | |
| 775 | /* COMMON_CPUID_INDEX_80000007. */ |
| 776 | |
| 777 | /* EDX. */ |
| 778 | #define reg_INVARIANT_TSC edx |
| 779 | |
| 780 | /* COMMON_CPUID_INDEX_80000008. */ |
| 781 | |
| 782 | /* EBX. */ |
| 783 | #define reg_WBNOINVD ebx |
| 784 | |
| 785 | /* COMMON_CPUID_INDEX_7_ECX_1. */ |
| 786 | |
| 787 | /* EAX. */ |
| 788 | #define reg_AVX512_BF16 eax |
| 789 | |
| 790 | /* FEATURE_INDEX_2. */ |
| 791 | #define bit_arch_I586 (1u << 0) |
| 792 | #define bit_arch_I686 (1u << 1) |
| 793 | #define bit_arch_Fast_Rep_String (1u << 2) |
| 794 | #define bit_arch_Fast_Copy_Backward (1u << 3) |
| 795 | #define bit_arch_Fast_Unaligned_Load (1u << 4) |
| 796 | #define bit_arch_Fast_Unaligned_Copy (1u << 5) |
| 797 | #define bit_arch_Slow_BSF (1u << 6) |
| 798 | #define bit_arch_Slow_SSE4_2 (1u << 7) |
| 799 | #define bit_arch_AVX_Fast_Unaligned_Load (1u << 8) |
| 800 | #define bit_arch_Prefer_MAP_32BIT_EXEC (1u << 9) |
| 801 | #define bit_arch_Prefer_PMINUB_for_stringop (1u << 10) |
| 802 | #define bit_arch_Prefer_No_VZEROUPPER (1u << 11) |
| 803 | #define bit_arch_Prefer_ERMS (1u << 12) |
| 804 | #define bit_arch_Prefer_FSRM (1u << 13) |
| 805 | #define bit_arch_Prefer_No_AVX512 (1u << 14) |
| 806 | #define bit_arch_MathVec_Prefer_No_AVX512 (1u << 15) |
| 807 | |
| 808 | #define index_arch_Fast_Rep_String PREFERRED_FEATURE_INDEX_1 |
| 809 | #define index_arch_Fast_Copy_Backward PREFERRED_FEATURE_INDEX_1 |
| 810 | #define index_arch_Slow_BSF PREFERRED_FEATURE_INDEX_1 |
| 811 | #define index_arch_Fast_Unaligned_Load PREFERRED_FEATURE_INDEX_1 |
| 812 | #define index_arch_Prefer_PMINUB_for_stringop PREFERRED_FEATURE_INDEX_1 |
| 813 | #define index_arch_Fast_Unaligned_Copy PREFERRED_FEATURE_INDEX_1 |
| 814 | #define index_arch_I586 PREFERRED_FEATURE_INDEX_1 |
| 815 | #define index_arch_I686 PREFERRED_FEATURE_INDEX_1 |
| 816 | #define index_arch_Slow_SSE4_2 PREFERRED_FEATURE_INDEX_1 |
| 817 | #define index_arch_AVX_Fast_Unaligned_Load PREFERRED_FEATURE_INDEX_1 |
| 818 | #define index_arch_Prefer_MAP_32BIT_EXEC PREFERRED_FEATURE_INDEX_1 |
| 819 | #define index_arch_Prefer_No_VZEROUPPER PREFERRED_FEATURE_INDEX_1 |
| 820 | #define index_arch_Prefer_ERMS PREFERRED_FEATURE_INDEX_1 |
| 821 | #define index_arch_Prefer_No_AVX512 PREFERRED_FEATURE_INDEX_1 |
| 822 | #define index_arch_MathVec_Prefer_No_AVX512 PREFERRED_FEATURE_INDEX_1 |
| 823 | #define index_arch_Prefer_FSRM PREFERRED_FEATURE_INDEX_1 |
| 824 | |
| 825 | /* XCR0 Feature flags. */ |
| 826 | #define bit_XMM_state (1u << 1) |
| 827 | #define bit_YMM_state (1u << 2) |
| 828 | #define bit_Opmask_state (1u << 5) |
| 829 | #define bit_ZMM0_15_state (1u << 6) |
| 830 | #define bit_ZMM16_31_state (1u << 7) |
| 831 | #define bit_XTILECFG_state (1u << 17) |
| 832 | #define bit_XTILEDATA_state (1u << 18) |
| 833 | |
| 834 | # if defined (_LIBC) && !IS_IN (nonlib) |
| 835 | /* Unused for x86. */ |
| 836 | # define INIT_ARCH() |
| 837 | # define __get_cpu_features() (&GLRO(dl_x86_cpu_features)) |
| 838 | # endif |
| 839 | |
| 840 | #ifdef __x86_64__ |
| 841 | # define HAS_CPUID 1 |
| 842 | #elif (defined __i586__ || defined __pentium__ \ |
| 843 | || defined __geode__ || defined __k6__) |
| 844 | # define HAS_CPUID 1 |
| 845 | # define HAS_I586 1 |
| 846 | # define HAS_I686 HAS_ARCH_FEATURE (I686) |
| 847 | #elif defined __i486__ |
| 848 | # define HAS_CPUID 0 |
| 849 | # define HAS_I586 HAS_ARCH_FEATURE (I586) |
| 850 | # define HAS_I686 HAS_ARCH_FEATURE (I686) |
| 851 | #else |
| 852 | # define HAS_CPUID 1 |
| 853 | # define HAS_I586 1 |
| 854 | # define HAS_I686 1 |
| 855 | #endif |
| 856 | |
| 857 | #endif /* cpu_features_h */ |
| 858 | |