1/* Initialize CPU feature data.
2 This file is part of the GNU C Library.
3 Copyright (C) 2008-2019 Free Software Foundation, Inc.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <http://www.gnu.org/licenses/>. */
18
19#include <cpuid.h>
20#include <cpu-features.h>
21#include <dl-hwcap.h>
22#include <libc-pointer-arith.h>
23
24#if HAVE_TUNABLES
25# define TUNABLE_NAMESPACE cpu
26# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */
27# include <elf/dl-tunables.h>
28
29extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *)
30 attribute_hidden;
31
32# if CET_ENABLED
33extern void TUNABLE_CALLBACK (set_x86_ibt) (tunable_val_t *)
34 attribute_hidden;
35extern void TUNABLE_CALLBACK (set_x86_shstk) (tunable_val_t *)
36 attribute_hidden;
37# endif
38#endif
39
40#if CET_ENABLED
41# include <dl-cet.h>
42# include <cet-tunables.h>
43#endif
44
45static void
46get_extended_indices (struct cpu_features *cpu_features)
47{
48 unsigned int eax, ebx, ecx, edx;
49 __cpuid (0x80000000, eax, ebx, ecx, edx);
50 if (eax >= 0x80000001)
51 __cpuid (0x80000001,
52 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].eax,
53 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ebx,
54 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ecx,
55 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].edx);
56 if (eax >= 0x80000007)
57 __cpuid (0x80000007,
58 cpu_features->cpuid[COMMON_CPUID_INDEX_80000007].eax,
59 cpu_features->cpuid[COMMON_CPUID_INDEX_80000007].ebx,
60 cpu_features->cpuid[COMMON_CPUID_INDEX_80000007].ecx,
61 cpu_features->cpuid[COMMON_CPUID_INDEX_80000007].edx);
62 if (eax >= 0x80000008)
63 __cpuid (0x80000008,
64 cpu_features->cpuid[COMMON_CPUID_INDEX_80000008].eax,
65 cpu_features->cpuid[COMMON_CPUID_INDEX_80000008].ebx,
66 cpu_features->cpuid[COMMON_CPUID_INDEX_80000008].ecx,
67 cpu_features->cpuid[COMMON_CPUID_INDEX_80000008].edx);
68}
69
70static void
71get_common_indices (struct cpu_features *cpu_features,
72 unsigned int *family, unsigned int *model,
73 unsigned int *extended_model, unsigned int *stepping)
74{
75 if (family)
76 {
77 unsigned int eax;
78 __cpuid (1, eax, cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx,
79 cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx,
80 cpu_features->cpuid[COMMON_CPUID_INDEX_1].edx);
81 cpu_features->cpuid[COMMON_CPUID_INDEX_1].eax = eax;
82 *family = (eax >> 8) & 0x0f;
83 *model = (eax >> 4) & 0x0f;
84 *extended_model = (eax >> 12) & 0xf0;
85 *stepping = eax & 0x0f;
86 if (*family == 0x0f)
87 {
88 *family += (eax >> 20) & 0xff;
89 *model += *extended_model;
90 }
91 }
92
93 if (cpu_features->basic.max_cpuid >= 7)
94 __cpuid_count (7, 0,
95 cpu_features->cpuid[COMMON_CPUID_INDEX_7].eax,
96 cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx,
97 cpu_features->cpuid[COMMON_CPUID_INDEX_7].ecx,
98 cpu_features->cpuid[COMMON_CPUID_INDEX_7].edx);
99
100 if (cpu_features->basic.max_cpuid >= 0xd)
101 __cpuid_count (0xd, 1,
102 cpu_features->cpuid[COMMON_CPUID_INDEX_D_ECX_1].eax,
103 cpu_features->cpuid[COMMON_CPUID_INDEX_D_ECX_1].ebx,
104 cpu_features->cpuid[COMMON_CPUID_INDEX_D_ECX_1].ecx,
105 cpu_features->cpuid[COMMON_CPUID_INDEX_D_ECX_1].edx);
106
107 /* Can we call xgetbv? */
108 if (CPU_FEATURES_CPU_P (cpu_features, OSXSAVE))
109 {
110 unsigned int xcrlow;
111 unsigned int xcrhigh;
112 asm ("xgetbv" : "=a" (xcrlow), "=d" (xcrhigh) : "c" (0));
113 /* Is YMM and XMM state usable? */
114 if ((xcrlow & (bit_YMM_state | bit_XMM_state)) ==
115 (bit_YMM_state | bit_XMM_state))
116 {
117 /* Determine if AVX is usable. */
118 if (CPU_FEATURES_CPU_P (cpu_features, AVX))
119 {
120 cpu_features->feature[index_arch_AVX_Usable]
121 |= bit_arch_AVX_Usable;
122 /* The following features depend on AVX being usable. */
123 /* Determine if AVX2 is usable. */
124 if (CPU_FEATURES_CPU_P (cpu_features, AVX2))
125 {
126 cpu_features->feature[index_arch_AVX2_Usable]
127 |= bit_arch_AVX2_Usable;
128
129 /* Unaligned load with 256-bit AVX registers are faster on
130 Intel/AMD processors with AVX2. */
131 cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
132 |= bit_arch_AVX_Fast_Unaligned_Load;
133 }
134 /* Determine if FMA is usable. */
135 if (CPU_FEATURES_CPU_P (cpu_features, FMA))
136 cpu_features->feature[index_arch_FMA_Usable]
137 |= bit_arch_FMA_Usable;
138 /* Determine if VAES is usable. */
139 if (CPU_FEATURES_CPU_P (cpu_features, VAES))
140 cpu_features->feature[index_arch_VAES_Usable]
141 |= bit_arch_VAES_Usable;
142 /* Determine if VPCLMULQDQ is usable. */
143 if (CPU_FEATURES_CPU_P (cpu_features, VPCLMULQDQ))
144 cpu_features->feature[index_arch_VPCLMULQDQ_Usable]
145 |= bit_arch_VPCLMULQDQ_Usable;
146 /* Determine if XOP is usable. */
147 if (CPU_FEATURES_CPU_P (cpu_features, XOP))
148 cpu_features->feature[index_arch_XOP_Usable]
149 |= bit_arch_XOP_Usable;
150 }
151
152 /* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
153 ZMM16-ZMM31 state are enabled. */
154 if ((xcrlow & (bit_Opmask_state | bit_ZMM0_15_state
155 | bit_ZMM16_31_state)) ==
156 (bit_Opmask_state | bit_ZMM0_15_state | bit_ZMM16_31_state))
157 {
158 /* Determine if AVX512F is usable. */
159 if (CPU_FEATURES_CPU_P (cpu_features, AVX512F))
160 {
161 cpu_features->feature[index_arch_AVX512F_Usable]
162 |= bit_arch_AVX512F_Usable;
163 /* Determine if AVX512CD is usable. */
164 if (CPU_FEATURES_CPU_P (cpu_features, AVX512CD))
165 cpu_features->feature[index_arch_AVX512CD_Usable]
166 |= bit_arch_AVX512CD_Usable;
167 /* Determine if AVX512ER is usable. */
168 if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
169 cpu_features->feature[index_arch_AVX512ER_Usable]
170 |= bit_arch_AVX512ER_Usable;
171 /* Determine if AVX512PF is usable. */
172 if (CPU_FEATURES_CPU_P (cpu_features, AVX512PF))
173 cpu_features->feature[index_arch_AVX512PF_Usable]
174 |= bit_arch_AVX512PF_Usable;
175 /* Determine if AVX512VL is usable. */
176 if (CPU_FEATURES_CPU_P (cpu_features, AVX512VL))
177 cpu_features->feature[index_arch_AVX512VL_Usable]
178 |= bit_arch_AVX512VL_Usable;
179 /* Determine if AVX512DQ is usable. */
180 if (CPU_FEATURES_CPU_P (cpu_features, AVX512DQ))
181 cpu_features->feature[index_arch_AVX512DQ_Usable]
182 |= bit_arch_AVX512DQ_Usable;
183 /* Determine if AVX512BW is usable. */
184 if (CPU_FEATURES_CPU_P (cpu_features, AVX512BW))
185 cpu_features->feature[index_arch_AVX512BW_Usable]
186 |= bit_arch_AVX512BW_Usable;
187 /* Determine if AVX512_4FMAPS is usable. */
188 if (CPU_FEATURES_CPU_P (cpu_features, AVX512_4FMAPS))
189 cpu_features->feature[index_arch_AVX512_4FMAPS_Usable]
190 |= bit_arch_AVX512_4FMAPS_Usable;
191 /* Determine if AVX512_4VNNIW is usable. */
192 if (CPU_FEATURES_CPU_P (cpu_features, AVX512_4VNNIW))
193 cpu_features->feature[index_arch_AVX512_4VNNIW_Usable]
194 |= bit_arch_AVX512_4VNNIW_Usable;
195 /* Determine if AVX512_BITALG is usable. */
196 if (CPU_FEATURES_CPU_P (cpu_features, AVX512_BITALG))
197 cpu_features->feature[index_arch_AVX512_BITALG_Usable]
198 |= bit_arch_AVX512_BITALG_Usable;
199 /* Determine if AVX512_IFMA is usable. */
200 if (CPU_FEATURES_CPU_P (cpu_features, AVX512_IFMA))
201 cpu_features->feature[index_arch_AVX512_IFMA_Usable]
202 |= bit_arch_AVX512_IFMA_Usable;
203 /* Determine if AVX512_VBMI is usable. */
204 if (CPU_FEATURES_CPU_P (cpu_features, AVX512_VBMI))
205 cpu_features->feature[index_arch_AVX512_VBMI_Usable]
206 |= bit_arch_AVX512_VBMI_Usable;
207 /* Determine if AVX512_VBMI2 is usable. */
208 if (CPU_FEATURES_CPU_P (cpu_features, AVX512_VBMI2))
209 cpu_features->feature[index_arch_AVX512_VBMI2_Usable]
210 |= bit_arch_AVX512_VBMI2_Usable;
211 /* Determine if is AVX512_VNNI usable. */
212 if (CPU_FEATURES_CPU_P (cpu_features, AVX512_VNNI))
213 cpu_features->feature[index_arch_AVX512_VNNI_Usable]
214 |= bit_arch_AVX512_VNNI_Usable;
215 /* Determine if AVX512_VPOPCNTDQ is usable. */
216 if (CPU_FEATURES_CPU_P (cpu_features, AVX512_VPOPCNTDQ))
217 cpu_features->feature[index_arch_AVX512_VPOPCNTDQ_Usable]
218 |= bit_arch_AVX512_VPOPCNTDQ_Usable;
219 }
220 }
221 }
222
223 /* For _dl_runtime_resolve, set xsave_state_size to xsave area
224 size + integer register save size and align it to 64 bytes. */
225 if (cpu_features->basic.max_cpuid >= 0xd)
226 {
227 unsigned int eax, ebx, ecx, edx;
228
229 __cpuid_count (0xd, 0, eax, ebx, ecx, edx);
230 if (ebx != 0)
231 {
232 unsigned int xsave_state_full_size
233 = ALIGN_UP (ebx + STATE_SAVE_OFFSET, 64);
234
235 cpu_features->xsave_state_size
236 = xsave_state_full_size;
237 cpu_features->xsave_state_full_size
238 = xsave_state_full_size;
239
240 /* Check if XSAVEC is available. */
241 if (CPU_FEATURES_CPU_P (cpu_features, XSAVEC))
242 {
243 unsigned int xstate_comp_offsets[32];
244 unsigned int xstate_comp_sizes[32];
245 unsigned int i;
246
247 xstate_comp_offsets[0] = 0;
248 xstate_comp_offsets[1] = 160;
249 xstate_comp_offsets[2] = 576;
250 xstate_comp_sizes[0] = 160;
251 xstate_comp_sizes[1] = 256;
252
253 for (i = 2; i < 32; i++)
254 {
255 if ((STATE_SAVE_MASK & (1 << i)) != 0)
256 {
257 __cpuid_count (0xd, i, eax, ebx, ecx, edx);
258 xstate_comp_sizes[i] = eax;
259 }
260 else
261 {
262 ecx = 0;
263 xstate_comp_sizes[i] = 0;
264 }
265
266 if (i > 2)
267 {
268 xstate_comp_offsets[i]
269 = (xstate_comp_offsets[i - 1]
270 + xstate_comp_sizes[i -1]);
271 if ((ecx & (1 << 1)) != 0)
272 xstate_comp_offsets[i]
273 = ALIGN_UP (xstate_comp_offsets[i], 64);
274 }
275 }
276
277 /* Use XSAVEC. */
278 unsigned int size
279 = xstate_comp_offsets[31] + xstate_comp_sizes[31];
280 if (size)
281 {
282 cpu_features->xsave_state_size
283 = ALIGN_UP (size + STATE_SAVE_OFFSET, 64);
284 cpu_features->feature[index_arch_XSAVEC_Usable]
285 |= bit_arch_XSAVEC_Usable;
286 }
287 }
288 }
289 }
290 }
291}
292
293_Static_assert (((index_arch_Fast_Unaligned_Load
294 == index_arch_Fast_Unaligned_Copy)
295 && (index_arch_Fast_Unaligned_Load
296 == index_arch_Prefer_PMINUB_for_stringop)
297 && (index_arch_Fast_Unaligned_Load
298 == index_arch_Slow_SSE4_2)
299 && (index_arch_Fast_Unaligned_Load
300 == index_arch_Fast_Rep_String)
301 && (index_arch_Fast_Unaligned_Load
302 == index_arch_Fast_Copy_Backward)),
303 "Incorrect index_arch_Fast_Unaligned_Load");
304
305static inline void
306init_cpu_features (struct cpu_features *cpu_features)
307{
308 unsigned int ebx, ecx, edx;
309 unsigned int family = 0;
310 unsigned int model = 0;
311 unsigned int stepping = 0;
312 enum cpu_features_kind kind;
313
314#if !HAS_CPUID
315 if (__get_cpuid_max (0, 0) == 0)
316 {
317 kind = arch_kind_other;
318 goto no_cpuid;
319 }
320#endif
321
322 __cpuid (0, cpu_features->basic.max_cpuid, ebx, ecx, edx);
323
324 /* This spells out "GenuineIntel". */
325 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
326 {
327 unsigned int extended_model;
328
329 kind = arch_kind_intel;
330
331 get_common_indices (cpu_features, &family, &model, &extended_model,
332 &stepping);
333
334 get_extended_indices (cpu_features);
335
336 if (family == 0x06)
337 {
338 model += extended_model;
339 switch (model)
340 {
341 case 0x1c:
342 case 0x26:
343 /* BSF is slow on Atom. */
344 cpu_features->feature[index_arch_Slow_BSF]
345 |= bit_arch_Slow_BSF;
346 break;
347
348 case 0x57:
349 /* Knights Landing. Enable Silvermont optimizations. */
350
351 case 0x5c:
352 case 0x5f:
353 /* Unaligned load versions are faster than SSSE3
354 on Goldmont. */
355
356 case 0x4c:
357 /* Airmont is a die shrink of Silvermont. */
358
359 case 0x37:
360 case 0x4a:
361 case 0x4d:
362 case 0x5a:
363 case 0x5d:
364 /* Unaligned load versions are faster than SSSE3
365 on Silvermont. */
366 cpu_features->feature[index_arch_Fast_Unaligned_Load]
367 |= (bit_arch_Fast_Unaligned_Load
368 | bit_arch_Fast_Unaligned_Copy
369 | bit_arch_Prefer_PMINUB_for_stringop
370 | bit_arch_Slow_SSE4_2);
371 break;
372
373 default:
374 /* Unknown family 0x06 processors. Assuming this is one
375 of Core i3/i5/i7 processors if AVX is available. */
376 if (!CPU_FEATURES_CPU_P (cpu_features, AVX))
377 break;
378
379 case 0x1a:
380 case 0x1e:
381 case 0x1f:
382 case 0x25:
383 case 0x2c:
384 case 0x2e:
385 case 0x2f:
386 /* Rep string instructions, unaligned load, unaligned copy,
387 and pminub are fast on Intel Core i3, i5 and i7. */
388 cpu_features->feature[index_arch_Fast_Rep_String]
389 |= (bit_arch_Fast_Rep_String
390 | bit_arch_Fast_Unaligned_Load
391 | bit_arch_Fast_Unaligned_Copy
392 | bit_arch_Prefer_PMINUB_for_stringop);
393 break;
394 }
395
396 /* Disable TSX on some Haswell processors to avoid TSX on kernels that
397 weren't updated with the latest microcode package (which disables
398 broken feature by default). */
399 switch (model)
400 {
401 case 0x3f:
402 /* Xeon E7 v3 with stepping >= 4 has working TSX. */
403 if (stepping >= 4)
404 break;
405 case 0x3c:
406 case 0x45:
407 case 0x46:
408 /* Disable Intel TSX on Haswell processors (except Xeon E7 v3
409 with stepping >= 4) to avoid TSX on kernels that weren't
410 updated with the latest microcode package (which disables
411 broken feature by default). */
412 cpu_features->cpuid[index_cpu_RTM].reg_RTM &= ~bit_cpu_RTM;
413 break;
414 }
415 }
416
417
418 /* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER
419 if AVX512ER is available. Don't use AVX512 to avoid lower CPU
420 frequency if AVX512ER isn't available. */
421 if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
422 cpu_features->feature[index_arch_Prefer_No_VZEROUPPER]
423 |= bit_arch_Prefer_No_VZEROUPPER;
424 else
425 cpu_features->feature[index_arch_Prefer_No_AVX512]
426 |= bit_arch_Prefer_No_AVX512;
427 }
428 /* This spells out "AuthenticAMD" or "HygonGenuine". */
429 else if ((ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
430 || (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e))
431 {
432 unsigned int extended_model;
433
434 kind = arch_kind_amd;
435
436 get_common_indices (cpu_features, &family, &model, &extended_model,
437 &stepping);
438
439 get_extended_indices (cpu_features);
440
441 ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx;
442
443 if (HAS_ARCH_FEATURE (AVX_Usable))
444 {
445 /* Since the FMA4 bit is in COMMON_CPUID_INDEX_80000001 and
446 FMA4 requires AVX, determine if FMA4 is usable here. */
447 if (CPU_FEATURES_CPU_P (cpu_features, FMA4))
448 cpu_features->feature[index_arch_FMA4_Usable]
449 |= bit_arch_FMA4_Usable;
450 }
451
452 if (family == 0x15)
453 {
454 /* "Excavator" */
455 if (model >= 0x60 && model <= 0x7f)
456 {
457 cpu_features->feature[index_arch_Fast_Unaligned_Load]
458 |= (bit_arch_Fast_Unaligned_Load
459 | bit_arch_Fast_Copy_Backward);
460
461 /* Unaligned AVX loads are slower.*/
462 cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
463 &= ~bit_arch_AVX_Fast_Unaligned_Load;
464 }
465 }
466 }
467 else
468 {
469 kind = arch_kind_other;
470 get_common_indices (cpu_features, NULL, NULL, NULL, NULL);
471 }
472
473 /* Support i586 if CX8 is available. */
474 if (CPU_FEATURES_CPU_P (cpu_features, CX8))
475 cpu_features->feature[index_arch_I586] |= bit_arch_I586;
476
477 /* Support i686 if CMOV is available. */
478 if (CPU_FEATURES_CPU_P (cpu_features, CMOV))
479 cpu_features->feature[index_arch_I686] |= bit_arch_I686;
480
481#if !HAS_CPUID
482no_cpuid:
483#endif
484
485 cpu_features->basic.kind = kind;
486 cpu_features->basic.family = family;
487 cpu_features->basic.model = model;
488 cpu_features->basic.stepping = stepping;
489
490#if HAVE_TUNABLES
491 TUNABLE_GET (hwcaps, tunable_val_t *, TUNABLE_CALLBACK (set_hwcaps));
492 cpu_features->non_temporal_threshold
493 = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL);
494 cpu_features->data_cache_size
495 = TUNABLE_GET (x86_data_cache_size, long int, NULL);
496 cpu_features->shared_cache_size
497 = TUNABLE_GET (x86_shared_cache_size, long int, NULL);
498#endif
499
500 /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. */
501#if !HAVE_TUNABLES && defined SHARED
502 /* The glibc.cpu.hwcap_mask tunable is initialized already, so no need to do
503 this. */
504 GLRO(dl_hwcap_mask) = HWCAP_IMPORTANT;
505#endif
506
507#ifdef __x86_64__
508 GLRO(dl_hwcap) = HWCAP_X86_64;
509 if (cpu_features->basic.kind == arch_kind_intel)
510 {
511 const char *platform = NULL;
512
513 if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable)
514 && CPU_FEATURES_CPU_P (cpu_features, AVX512CD))
515 {
516 if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
517 {
518 if (CPU_FEATURES_CPU_P (cpu_features, AVX512PF))
519 platform = "xeon_phi";
520 }
521 else
522 {
523 if (CPU_FEATURES_CPU_P (cpu_features, AVX512BW)
524 && CPU_FEATURES_CPU_P (cpu_features, AVX512DQ)
525 && CPU_FEATURES_CPU_P (cpu_features, AVX512VL))
526 GLRO(dl_hwcap) |= HWCAP_X86_AVX512_1;
527 }
528 }
529
530 if (platform == NULL
531 && CPU_FEATURES_ARCH_P (cpu_features, AVX2_Usable)
532 && CPU_FEATURES_ARCH_P (cpu_features, FMA_Usable)
533 && CPU_FEATURES_CPU_P (cpu_features, BMI1)
534 && CPU_FEATURES_CPU_P (cpu_features, BMI2)
535 && CPU_FEATURES_CPU_P (cpu_features, LZCNT)
536 && CPU_FEATURES_CPU_P (cpu_features, MOVBE)
537 && CPU_FEATURES_CPU_P (cpu_features, POPCNT))
538 platform = "haswell";
539
540 if (platform != NULL)
541 GLRO(dl_platform) = platform;
542 }
543#else
544 GLRO(dl_hwcap) = 0;
545 if (CPU_FEATURES_CPU_P (cpu_features, SSE2))
546 GLRO(dl_hwcap) |= HWCAP_X86_SSE2;
547
548 if (CPU_FEATURES_ARCH_P (cpu_features, I686))
549 GLRO(dl_platform) = "i686";
550 else if (CPU_FEATURES_ARCH_P (cpu_features, I586))
551 GLRO(dl_platform) = "i586";
552#endif
553
554#if CET_ENABLED
555# if HAVE_TUNABLES
556 TUNABLE_GET (x86_ibt, tunable_val_t *,
557 TUNABLE_CALLBACK (set_x86_ibt));
558 TUNABLE_GET (x86_shstk, tunable_val_t *,
559 TUNABLE_CALLBACK (set_x86_shstk));
560# endif
561
562 /* Check CET status. */
563 unsigned int cet_status = get_cet_status ();
564
565 if (cet_status)
566 {
567 GL(dl_x86_feature_1)[0] = cet_status;
568
569# ifndef SHARED
570 /* Check if IBT and SHSTK are enabled by kernel. */
571 if ((cet_status & GNU_PROPERTY_X86_FEATURE_1_IBT)
572 || (cet_status & GNU_PROPERTY_X86_FEATURE_1_SHSTK))
573 {
574 /* Disable IBT and/or SHSTK if they are enabled by kernel, but
575 disabled by environment variable:
576
577 GLIBC_TUNABLES=glibc.cpu.hwcaps=-IBT,-SHSTK
578 */
579 unsigned int cet_feature = 0;
580 if (!HAS_CPU_FEATURE (IBT))
581 cet_feature |= GNU_PROPERTY_X86_FEATURE_1_IBT;
582 if (!HAS_CPU_FEATURE (SHSTK))
583 cet_feature |= GNU_PROPERTY_X86_FEATURE_1_SHSTK;
584
585 if (cet_feature)
586 {
587 int res = dl_cet_disable_cet (cet_feature);
588
589 /* Clear the disabled bits in dl_x86_feature_1. */
590 if (res == 0)
591 GL(dl_x86_feature_1)[0] &= ~cet_feature;
592 }
593
594 /* Lock CET if IBT or SHSTK is enabled in executable. Don't
595 lock CET if SHSTK is enabled permissively. */
596 if (((GL(dl_x86_feature_1)[1] >> CET_MAX)
597 & ((1 << CET_MAX) - 1))
598 != CET_PERMISSIVE)
599 dl_cet_lock_cet ();
600 }
601# endif
602 }
603#endif
604}
605