1/* Initialize CPU feature data.
2 This file is part of the GNU C Library.
3 Copyright (C) 2008-2018 Free Software Foundation, Inc.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <http://www.gnu.org/licenses/>. */
18
19#include <cpuid.h>
20#include <cpu-features.h>
21#include <dl-hwcap.h>
22#include <libc-pointer-arith.h>
23
24#if HAVE_TUNABLES
25# define TUNABLE_NAMESPACE tune
26# include <unistd.h> /* Get STDOUT_FILENO for _dl_printf. */
27# include <elf/dl-tunables.h>
28
29extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *)
30 attribute_hidden;
31
32# if CET_ENABLED
33extern void TUNABLE_CALLBACK (set_x86_ibt) (tunable_val_t *)
34 attribute_hidden;
35extern void TUNABLE_CALLBACK (set_x86_shstk) (tunable_val_t *)
36 attribute_hidden;
37# endif
38#endif
39
40#if CET_ENABLED
41# include <dl-cet.h>
42# include <cet-tunables.h>
43#endif
44
45static void
46get_extended_indices (struct cpu_features *cpu_features)
47{
48 unsigned int eax, ebx, ecx, edx;
49 __cpuid (0x80000000, eax, ebx, ecx, edx);
50 if (eax >= 0x80000001)
51 __cpuid (0x80000001,
52 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].eax,
53 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ebx,
54 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].ecx,
55 cpu_features->cpuid[COMMON_CPUID_INDEX_80000001].edx);
56
57}
58
59static void
60get_common_indeces (struct cpu_features *cpu_features,
61 unsigned int *family, unsigned int *model,
62 unsigned int *extended_model, unsigned int *stepping)
63{
64 if (family)
65 {
66 unsigned int eax;
67 __cpuid (1, eax, cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx,
68 cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx,
69 cpu_features->cpuid[COMMON_CPUID_INDEX_1].edx);
70 cpu_features->cpuid[COMMON_CPUID_INDEX_1].eax = eax;
71 *family = (eax >> 8) & 0x0f;
72 *model = (eax >> 4) & 0x0f;
73 *extended_model = (eax >> 12) & 0xf0;
74 *stepping = eax & 0x0f;
75 if (*family == 0x0f)
76 {
77 *family += (eax >> 20) & 0xff;
78 *model += *extended_model;
79 }
80 }
81
82 if (cpu_features->max_cpuid >= 7)
83 __cpuid_count (7, 0,
84 cpu_features->cpuid[COMMON_CPUID_INDEX_7].eax,
85 cpu_features->cpuid[COMMON_CPUID_INDEX_7].ebx,
86 cpu_features->cpuid[COMMON_CPUID_INDEX_7].ecx,
87 cpu_features->cpuid[COMMON_CPUID_INDEX_7].edx);
88
89 /* Can we call xgetbv? */
90 if (CPU_FEATURES_CPU_P (cpu_features, OSXSAVE))
91 {
92 unsigned int xcrlow;
93 unsigned int xcrhigh;
94 asm ("xgetbv" : "=a" (xcrlow), "=d" (xcrhigh) : "c" (0));
95 /* Is YMM and XMM state usable? */
96 if ((xcrlow & (bit_YMM_state | bit_XMM_state)) ==
97 (bit_YMM_state | bit_XMM_state))
98 {
99 /* Determine if AVX is usable. */
100 if (CPU_FEATURES_CPU_P (cpu_features, AVX))
101 {
102 cpu_features->feature[index_arch_AVX_Usable]
103 |= bit_arch_AVX_Usable;
104 /* The following features depend on AVX being usable. */
105 /* Determine if AVX2 is usable. */
106 if (CPU_FEATURES_CPU_P (cpu_features, AVX2))
107 {
108 cpu_features->feature[index_arch_AVX2_Usable]
109 |= bit_arch_AVX2_Usable;
110
111 /* Unaligned load with 256-bit AVX registers are faster on
112 Intel/AMD processors with AVX2. */
113 cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
114 |= bit_arch_AVX_Fast_Unaligned_Load;
115 }
116 /* Determine if FMA is usable. */
117 if (CPU_FEATURES_CPU_P (cpu_features, FMA))
118 cpu_features->feature[index_arch_FMA_Usable]
119 |= bit_arch_FMA_Usable;
120 }
121
122 /* Check if OPMASK state, upper 256-bit of ZMM0-ZMM15 and
123 ZMM16-ZMM31 state are enabled. */
124 if ((xcrlow & (bit_Opmask_state | bit_ZMM0_15_state
125 | bit_ZMM16_31_state)) ==
126 (bit_Opmask_state | bit_ZMM0_15_state | bit_ZMM16_31_state))
127 {
128 /* Determine if AVX512F is usable. */
129 if (CPU_FEATURES_CPU_P (cpu_features, AVX512F))
130 {
131 cpu_features->feature[index_arch_AVX512F_Usable]
132 |= bit_arch_AVX512F_Usable;
133 /* Determine if AVX512DQ is usable. */
134 if (CPU_FEATURES_CPU_P (cpu_features, AVX512DQ))
135 cpu_features->feature[index_arch_AVX512DQ_Usable]
136 |= bit_arch_AVX512DQ_Usable;
137 }
138 }
139 }
140
141 /* For _dl_runtime_resolve, set xsave_state_size to xsave area
142 size + integer register save size and align it to 64 bytes. */
143 if (cpu_features->max_cpuid >= 0xd)
144 {
145 unsigned int eax, ebx, ecx, edx;
146
147 __cpuid_count (0xd, 0, eax, ebx, ecx, edx);
148 if (ebx != 0)
149 {
150 unsigned int xsave_state_full_size
151 = ALIGN_UP (ebx + STATE_SAVE_OFFSET, 64);
152
153 cpu_features->xsave_state_size
154 = xsave_state_full_size;
155 cpu_features->xsave_state_full_size
156 = xsave_state_full_size;
157
158 __cpuid_count (0xd, 1, eax, ebx, ecx, edx);
159
160 /* Check if XSAVEC is available. */
161 if ((eax & (1 << 1)) != 0)
162 {
163 unsigned int xstate_comp_offsets[32];
164 unsigned int xstate_comp_sizes[32];
165 unsigned int i;
166
167 xstate_comp_offsets[0] = 0;
168 xstate_comp_offsets[1] = 160;
169 xstate_comp_offsets[2] = 576;
170 xstate_comp_sizes[0] = 160;
171 xstate_comp_sizes[1] = 256;
172
173 for (i = 2; i < 32; i++)
174 {
175 if ((STATE_SAVE_MASK & (1 << i)) != 0)
176 {
177 __cpuid_count (0xd, i, eax, ebx, ecx, edx);
178 xstate_comp_sizes[i] = eax;
179 }
180 else
181 {
182 ecx = 0;
183 xstate_comp_sizes[i] = 0;
184 }
185
186 if (i > 2)
187 {
188 xstate_comp_offsets[i]
189 = (xstate_comp_offsets[i - 1]
190 + xstate_comp_sizes[i -1]);
191 if ((ecx & (1 << 1)) != 0)
192 xstate_comp_offsets[i]
193 = ALIGN_UP (xstate_comp_offsets[i], 64);
194 }
195 }
196
197 /* Use XSAVEC. */
198 unsigned int size
199 = xstate_comp_offsets[31] + xstate_comp_sizes[31];
200 if (size)
201 {
202 cpu_features->xsave_state_size
203 = ALIGN_UP (size + STATE_SAVE_OFFSET, 64);
204 cpu_features->feature[index_arch_XSAVEC_Usable]
205 |= bit_arch_XSAVEC_Usable;
206 }
207 }
208 }
209 }
210 }
211}
212
213static inline void
214init_cpu_features (struct cpu_features *cpu_features)
215{
216 unsigned int ebx, ecx, edx;
217 unsigned int family = 0;
218 unsigned int model = 0;
219 enum cpu_features_kind kind;
220
221#if !HAS_CPUID
222 if (__get_cpuid_max (0, 0) == 0)
223 {
224 kind = arch_kind_other;
225 goto no_cpuid;
226 }
227#endif
228
229 __cpuid (0, cpu_features->max_cpuid, ebx, ecx, edx);
230
231 /* This spells out "GenuineIntel". */
232 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
233 {
234 unsigned int extended_model, stepping;
235
236 kind = arch_kind_intel;
237
238 get_common_indeces (cpu_features, &family, &model, &extended_model,
239 &stepping);
240
241 get_extended_indices (cpu_features);
242
243 if (family == 0x06)
244 {
245 model += extended_model;
246 switch (model)
247 {
248 case 0x1c:
249 case 0x26:
250 /* BSF is slow on Atom. */
251 cpu_features->feature[index_arch_Slow_BSF]
252 |= bit_arch_Slow_BSF;
253 break;
254
255 case 0x57:
256 /* Knights Landing. Enable Silvermont optimizations. */
257
258 case 0x5c:
259 case 0x5f:
260 /* Unaligned load versions are faster than SSSE3
261 on Goldmont. */
262
263 case 0x4c:
264 /* Airmont is a die shrink of Silvermont. */
265
266 case 0x37:
267 case 0x4a:
268 case 0x4d:
269 case 0x5a:
270 case 0x5d:
271 /* Unaligned load versions are faster than SSSE3
272 on Silvermont. */
273#if index_arch_Fast_Unaligned_Load != index_arch_Prefer_PMINUB_for_stringop
274# error index_arch_Fast_Unaligned_Load != index_arch_Prefer_PMINUB_for_stringop
275#endif
276#if index_arch_Fast_Unaligned_Load != index_arch_Slow_SSE4_2
277# error index_arch_Fast_Unaligned_Load != index_arch_Slow_SSE4_2
278#endif
279#if index_arch_Fast_Unaligned_Load != index_arch_Fast_Unaligned_Copy
280# error index_arch_Fast_Unaligned_Load != index_arch_Fast_Unaligned_Copy
281#endif
282 cpu_features->feature[index_arch_Fast_Unaligned_Load]
283 |= (bit_arch_Fast_Unaligned_Load
284 | bit_arch_Fast_Unaligned_Copy
285 | bit_arch_Prefer_PMINUB_for_stringop
286 | bit_arch_Slow_SSE4_2);
287 break;
288
289 default:
290 /* Unknown family 0x06 processors. Assuming this is one
291 of Core i3/i5/i7 processors if AVX is available. */
292 if (!CPU_FEATURES_CPU_P (cpu_features, AVX))
293 break;
294
295 case 0x1a:
296 case 0x1e:
297 case 0x1f:
298 case 0x25:
299 case 0x2c:
300 case 0x2e:
301 case 0x2f:
302 /* Rep string instructions, unaligned load, unaligned copy,
303 and pminub are fast on Intel Core i3, i5 and i7. */
304#if index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Load
305# error index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Load
306#endif
307#if index_arch_Fast_Rep_String != index_arch_Prefer_PMINUB_for_stringop
308# error index_arch_Fast_Rep_String != index_arch_Prefer_PMINUB_for_stringop
309#endif
310#if index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Copy
311# error index_arch_Fast_Rep_String != index_arch_Fast_Unaligned_Copy
312#endif
313 cpu_features->feature[index_arch_Fast_Rep_String]
314 |= (bit_arch_Fast_Rep_String
315 | bit_arch_Fast_Unaligned_Load
316 | bit_arch_Fast_Unaligned_Copy
317 | bit_arch_Prefer_PMINUB_for_stringop);
318 break;
319
320 case 0x3f:
321 /* Xeon E7 v3 with stepping >= 4 has working TSX. */
322 if (stepping >= 4)
323 break;
324 case 0x3c:
325 case 0x45:
326 case 0x46:
327 /* Disable Intel TSX on Haswell processors (except Xeon E7 v3
328 with stepping >= 4) to avoid TSX on kernels that weren't
329 updated with the latest microcode package (which disables
330 broken feature by default). */
331 cpu_features->cpuid[index_cpu_RTM].reg_RTM &= ~bit_cpu_RTM;
332 break;
333 }
334 }
335
336
337 /* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER
338 if AVX512ER is available. Don't use AVX512 to avoid lower CPU
339 frequency if AVX512ER isn't available. */
340 if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
341 cpu_features->feature[index_arch_Prefer_No_VZEROUPPER]
342 |= bit_arch_Prefer_No_VZEROUPPER;
343 else
344 cpu_features->feature[index_arch_Prefer_No_AVX512]
345 |= bit_arch_Prefer_No_AVX512;
346 }
347 /* This spells out "AuthenticAMD". */
348 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
349 {
350 unsigned int extended_model, stepping;
351
352 kind = arch_kind_amd;
353
354 get_common_indeces (cpu_features, &family, &model, &extended_model,
355 &stepping);
356
357 get_extended_indices (cpu_features);
358
359 ecx = cpu_features->cpuid[COMMON_CPUID_INDEX_1].ecx;
360
361 if (HAS_ARCH_FEATURE (AVX_Usable))
362 {
363 /* Since the FMA4 bit is in COMMON_CPUID_INDEX_80000001 and
364 FMA4 requires AVX, determine if FMA4 is usable here. */
365 if (CPU_FEATURES_CPU_P (cpu_features, FMA4))
366 cpu_features->feature[index_arch_FMA4_Usable]
367 |= bit_arch_FMA4_Usable;
368 }
369
370 if (family == 0x15)
371 {
372#if index_arch_Fast_Unaligned_Load != index_arch_Fast_Copy_Backward
373# error index_arch_Fast_Unaligned_Load != index_arch_Fast_Copy_Backward
374#endif
375 /* "Excavator" */
376 if (model >= 0x60 && model <= 0x7f)
377 {
378 cpu_features->feature[index_arch_Fast_Unaligned_Load]
379 |= (bit_arch_Fast_Unaligned_Load
380 | bit_arch_Fast_Copy_Backward);
381
382 /* Unaligned AVX loads are slower.*/
383 cpu_features->feature[index_arch_AVX_Fast_Unaligned_Load]
384 &= ~bit_arch_AVX_Fast_Unaligned_Load;
385 }
386 }
387 }
388 else
389 {
390 kind = arch_kind_other;
391 get_common_indeces (cpu_features, NULL, NULL, NULL, NULL);
392 }
393
394 /* Support i586 if CX8 is available. */
395 if (CPU_FEATURES_CPU_P (cpu_features, CX8))
396 cpu_features->feature[index_arch_I586] |= bit_arch_I586;
397
398 /* Support i686 if CMOV is available. */
399 if (CPU_FEATURES_CPU_P (cpu_features, CMOV))
400 cpu_features->feature[index_arch_I686] |= bit_arch_I686;
401
402#if !HAS_CPUID
403no_cpuid:
404#endif
405
406 cpu_features->family = family;
407 cpu_features->model = model;
408 cpu_features->kind = kind;
409
410#if HAVE_TUNABLES
411 TUNABLE_GET (hwcaps, tunable_val_t *, TUNABLE_CALLBACK (set_hwcaps));
412 cpu_features->non_temporal_threshold
413 = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL);
414 cpu_features->data_cache_size
415 = TUNABLE_GET (x86_data_cache_size, long int, NULL);
416 cpu_features->shared_cache_size
417 = TUNABLE_GET (x86_shared_cache_size, long int, NULL);
418#endif
419
420 /* Reuse dl_platform, dl_hwcap and dl_hwcap_mask for x86. */
421#if !HAVE_TUNABLES && defined SHARED
422 /* The glibc.tune.hwcap_mask tunable is initialized already, so no need to do
423 this. */
424 GLRO(dl_hwcap_mask) = HWCAP_IMPORTANT;
425#endif
426
427#ifdef __x86_64__
428 GLRO(dl_hwcap) = HWCAP_X86_64;
429 if (cpu_features->kind == arch_kind_intel)
430 {
431 const char *platform = NULL;
432
433 if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable)
434 && CPU_FEATURES_CPU_P (cpu_features, AVX512CD))
435 {
436 if (CPU_FEATURES_CPU_P (cpu_features, AVX512ER))
437 {
438 if (CPU_FEATURES_CPU_P (cpu_features, AVX512PF))
439 platform = "xeon_phi";
440 }
441 else
442 {
443 if (CPU_FEATURES_CPU_P (cpu_features, AVX512BW)
444 && CPU_FEATURES_CPU_P (cpu_features, AVX512DQ)
445 && CPU_FEATURES_CPU_P (cpu_features, AVX512VL))
446 GLRO(dl_hwcap) |= HWCAP_X86_AVX512_1;
447 }
448 }
449
450 if (platform == NULL
451 && CPU_FEATURES_ARCH_P (cpu_features, AVX2_Usable)
452 && CPU_FEATURES_ARCH_P (cpu_features, FMA_Usable)
453 && CPU_FEATURES_CPU_P (cpu_features, BMI1)
454 && CPU_FEATURES_CPU_P (cpu_features, BMI2)
455 && CPU_FEATURES_CPU_P (cpu_features, LZCNT)
456 && CPU_FEATURES_CPU_P (cpu_features, MOVBE)
457 && CPU_FEATURES_CPU_P (cpu_features, POPCNT))
458 platform = "haswell";
459
460 if (platform != NULL)
461 GLRO(dl_platform) = platform;
462 }
463#else
464 GLRO(dl_hwcap) = 0;
465 if (CPU_FEATURES_CPU_P (cpu_features, SSE2))
466 GLRO(dl_hwcap) |= HWCAP_X86_SSE2;
467
468 if (CPU_FEATURES_ARCH_P (cpu_features, I686))
469 GLRO(dl_platform) = "i686";
470 else if (CPU_FEATURES_ARCH_P (cpu_features, I586))
471 GLRO(dl_platform) = "i586";
472#endif
473
474#if CET_ENABLED
475# if HAVE_TUNABLES
476 TUNABLE_GET (x86_ibt, tunable_val_t *,
477 TUNABLE_CALLBACK (set_x86_ibt));
478 TUNABLE_GET (x86_shstk, tunable_val_t *,
479 TUNABLE_CALLBACK (set_x86_shstk));
480# endif
481
482 /* Check CET status. */
483 unsigned int cet_status = get_cet_status ();
484
485 if (cet_status)
486 {
487 GL(dl_x86_feature_1)[0] = cet_status;
488
489# ifndef SHARED
490 /* Check if IBT and SHSTK are enabled by kernel. */
491 if ((cet_status & GNU_PROPERTY_X86_FEATURE_1_IBT)
492 || (cet_status & GNU_PROPERTY_X86_FEATURE_1_SHSTK))
493 {
494 /* Disable IBT and/or SHSTK if they are enabled by kernel, but
495 disabled by environment variable:
496
497 GLIBC_TUNABLES=glibc.tune.hwcaps=-IBT,-SHSTK
498 */
499 unsigned int cet_feature = 0;
500 if (!HAS_CPU_FEATURE (IBT))
501 cet_feature |= GNU_PROPERTY_X86_FEATURE_1_IBT;
502 if (!HAS_CPU_FEATURE (SHSTK))
503 cet_feature |= GNU_PROPERTY_X86_FEATURE_1_SHSTK;
504
505 if (cet_feature)
506 {
507 int res = dl_cet_disable_cet (cet_feature);
508
509 /* Clear the disabled bits in dl_x86_feature_1. */
510 if (res == 0)
511 GL(dl_x86_feature_1)[0] &= ~cet_feature;
512 }
513
514 /* Lock CET if IBT or SHSTK is enabled in executable. Don't
515 lock CET if SHSTK is enabled permissively. */
516 if (((GL(dl_x86_feature_1)[1] >> CET_MAX)
517 & ((1 << CET_MAX) - 1))
518 != CET_PERMISSIVE)
519 dl_cet_lock_cet ();
520 }
521# endif
522 }
523#endif
524}
525